Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Bhati, Ishwar; Chishti, Zeshan; Jacob, Bruce

doi:10.1109/islped.2013.6629295

Cited by 20 publications

(10 citation statements)

References 19 publications

(29 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In comparison, the row-level option reduces the opportunity to stay in PD mode and is not compatible with SR mode. Therefore, energy benefits of low power modes, quite significant in workloads with medium to high idle periods [23], are lost when row-level refreshes are employed.…”

Section: Benefits Of Auto-refresh Flexibilitymentioning

confidence: 99%

“…For instance, in namd, all-bank AR exhibits 22% and 38% DRAM energy improvement with PD and SR modes respectively. Furthermore, since our proposed refresh architecture provides the memory controller an ability to access and synchronize the refresh counter before and after SR mode, REFLEX techniques can be designed to reduce unnecessary refreshes in SR mode by programming low refresh rate, similar to the CO-FAST technique in [23]. Such techniques could further reduce refresh energy in SR mode.…”

Section: Reflex With Low Power Modesmentioning

confidence: 99%

“…Elastic Refresh [26] and Coordinated Refresh [23] rely on the ability to re-schedule refresh commands to overlap with periods of DRAM inactivity. Elastic refresh postpones up to eight refresh commands in high memory request phases of programs, and then issues the pending refreshes during idle memory phases at a faster rate to maintain the average refresh rate.…”

Section: Other Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Flexible auto-refresh

BhatiIshwar

ChishtiZeshan

LuShih-Lien

et al. 2015

SIGARCH Comput. Archit. News

Self Cite

View full text Add to dashboard Cite

DRAM cells require periodic refreshing to preserve data. In JEDEC DDRx devices, a refresh operation is performed via an auto-refresh command, which refreshes multiple rows in multiple banks simultaneously. The internal implementation of auto-refresh is completely opaque outside the DRAMall the memory controller can do is to instruct the DRAM to refresh itself -the DRAM handles all else, in particular determining which rows in which banks are to be refreshed. This is in conflict with a large body of research on reducing the refresh overhead, in which the memory controller needs fine-grained control over which regions of the memory are refreshed. For example, prior works exploit the fact that a subset of DRAM rows can be refreshed at a slower rate than other rows due to access rate or retention period variations. However, such row-granularity approaches cannot use the standard auto-refresh command, which refreshes an entire batch of rows at once and does not permit skipping of rows. Consequently, prior schemes are forced to use explicit sequences of activate (ACT) and precharge (PRE) operations to mimic row-level refreshing. The drawback is that, compared to using JEDEC's auto-refresh mechanism, using explicit ACT and PRE commands is inefficient, both in terms of performance and power.In this paper, we show that even when skipping a high percentage of refresh operations, existing row-granurality refresh techniques are mostly ineffective due to the inherent efficiency disparity between ACT/PRE and the JEDEC autorefresh mechanism. We propose a modification to the DRAM that extends its existing control-register access protocol to include the DRAM's internal refresh counter. We also introduce a new "dummy refresh" command that skips refresh operations and simply increments the internal counter. We show that these modifications allow a memory controller to reduce as many refreshes as in prior work,

show abstract

Section: Benefits Of Auto-refresh Flexibilitymentioning

confidence: 99%

Section: Reflex With Low Power Modesmentioning

confidence: 99%

Section: Other Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Flexible auto-refresh

BhatiIshwar

ChishtiZeshan

LuShih-Lien

et al. 2015

SIGARCH Comput. Archit. News

Self Cite

View full text Add to dashboard Cite

show abstract

“…Smart Refresh [Ghosh and Lee 2007] proposes to save energy by avoiding refreshes to recently accessed rows. In Coordinated Refresh [Bhati et al 2013], the authors propose scheduling refreshes when the DRAM device is in low-power mode and target achieving both energy savings and performance improvement. Exploiting the variation in data retention times of DRAM cells, RAPID [Venkatesan et al 2006] proposes a software method to place data in pages with high retention times and avoid unnecessary refreshes.…”

Section: Other Refresh Handling Workmentioning

confidence: 99%

Efgr

Tavva

Ravi

Mutyam

2014

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

High-density DRAM devices spend significant time refreshing the DRAM cells, leading to performance drop. The JEDEC DDR4 standard provides a Fine Granularity Refresh (FGR) feature to tackle refresh. Motivated by the observation that in FGR mode, only a few banks are involved, we propose an Enhanced FGR (EFGR) feature that introduces three optimizations to the basic FGR feature and exposes the bank-level parallelism within the rank even during the refresh. The first optimization decouples the nonrefreshing banks. The second and third optimizations determine the maximum number of nonrefreshing banks that can be active during refresh and selectively precharge the banks before refresh, respectively. Our simulation results show that the EFGR feature is able to recover almost 56.6% of the performance loss incurred due to refresh operations.

show abstract

“…There has been some research on reducing the overhead of DRAM by retention-aware refresh or refresh scheduling [3,4,5,6,7,8,9,10,11,12]. Research [4] proposed a RAAR technique to reduce refresh energy and performance degradation, only part of refresh bundles need a refresh in each refresh interval, while other refresh bundles can skip at least 50% of refresh operations.…”

Section: Introductionmentioning

confidence: 99%

Retention-Aware DRAM Auto-Refresh Scheme for Energy and Performance Efficiency

Cheng

Shen

2019

Micromachines

View full text Add to dashboard Cite

Dynamic random access memory (DRAM) circuits require periodic refresh operations to prevent data loss. As DRAM density increases, DRAM refresh overhead is even worse due to the increase of the refresh cycle time. However, because of few the cells in memory that have lower retention time, DRAM has to raise the refresh frequency to keep the data integrity, and hence produce unnecessary refreshes for the other normal cells, which results in a large refresh energy and performance delay of memory access. In this paper, we propose an integration scheme for DRAM refresh based on the retention-aware auto-refresh (RAAR) method and 2x granularity auto-refresh simultaneously. We also explain the corresponding modification need on memory controllers to support the proposed integration refresh scheme. With the given profile of weak cells distribution in memory banks, our integration scheme can choose the most appropriate refresh technique in each refresh time. Experimental results on different refresh cycle times show that the retention-aware refresh scheme can properly improve the system performance and have a great reduction in refresh energy. Especially when the number of weak cells increased due to the thermal effect of 3D-stacked architecture, our methodology still keeps the same performance and energy efficiency.

show abstract

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Cited by 20 publications

References 19 publications

Flexible auto-refresh

Flexible auto-refresh

Efgr

Retention-Aware DRAM Auto-Refresh Scheme for Energy and Performance Efficiency

Contact Info

Product

Resources

About