“…Oh et al observed the void formation in PCM devices using transmission electron microscopy (TEM) and the initial void location coincides with the maximum stress location. [ 17 ] In the HBW, the maximum stress was located at the edges of the heater near the GST/heater interface, which is consistent with the experimentally observed failure. [ 16 ] To make matters worse, the maximum stress location is also the maximum current density location.…”
“…[ 11–14 ] The stuck reset can be attributed to the failure of the GST/heater interface due to void formation or delamination, which mostly occurs at the GST/other material interface. [ 14–17 ] Delamination is an interfacial fracture and may be affected by the mechanical stress. In general, void formation in integrated circuits is the result of electromigration (EM).…”
Stuck reset is an open‐circuit failure that occurs in phase‐change memory (PCM) after repeated reset and set operations, that is, endurance cycling. Stuck reset is majorly caused by phase‐change stress, which is the mechanical stress induced during a reset operation due to the density difference between the amorphous and crystalline phases of the phase‐change material. This indicates that a reduction in phase‐change stress may improve the endurance characteristics of PCM. Herein, a simulation technique for the calculation of phase‐change stress using a finite‐element software is proposed. Subsequently, a comparative study of the endurance of different PCM device architectures is performed. The results reveal that the self‐heating architecture exhibits superior endurance compared to the heater‐based architecture. Furthermore, the void locations in the experiments coincide with the most highly stressed locations in the simulation.
“…Oh et al observed the void formation in PCM devices using transmission electron microscopy (TEM) and the initial void location coincides with the maximum stress location. [ 17 ] In the HBW, the maximum stress was located at the edges of the heater near the GST/heater interface, which is consistent with the experimentally observed failure. [ 16 ] To make matters worse, the maximum stress location is also the maximum current density location.…”
“…[ 11–14 ] The stuck reset can be attributed to the failure of the GST/heater interface due to void formation or delamination, which mostly occurs at the GST/other material interface. [ 14–17 ] Delamination is an interfacial fracture and may be affected by the mechanical stress. In general, void formation in integrated circuits is the result of electromigration (EM).…”
Stuck reset is an open‐circuit failure that occurs in phase‐change memory (PCM) after repeated reset and set operations, that is, endurance cycling. Stuck reset is majorly caused by phase‐change stress, which is the mechanical stress induced during a reset operation due to the density difference between the amorphous and crystalline phases of the phase‐change material. This indicates that a reduction in phase‐change stress may improve the endurance characteristics of PCM. Herein, a simulation technique for the calculation of phase‐change stress using a finite‐element software is proposed. Subsequently, a comparative study of the endurance of different PCM device architectures is performed. The results reveal that the self‐heating architecture exhibits superior endurance compared to the heater‐based architecture. Furthermore, the void locations in the experiments coincide with the most highly stressed locations in the simulation.
“…To explore the effects of this single-variant CuPt B ordering and APDBs on the electrical properties of the material, in situ biasing TEM electrical measurements were performed to analyze the difference on conductivity along specific directions at the nanoscale. For these measurements, a new set of samples was prepared by FIB. − Figure shows the schematic of the TEM-STM holder, where a sharp platinum tip was attached to the movable part of the STM holder, and both the GaInP samples and the STM tip were oriented perpendicular to the electron beam. , As can be seen in the figure, the protective Pt layer grown during FIB preparation was also etched by FIB in order to cut the Pt metallic path forcing the current to flow through the GaInP layer (see Figure S2b). During the measurements, the movable tip of the TEM-STM holder was positioned to contact directly on the GaInP:Sb layer to perform the electrical measurements solely through the GaInP layer.…”
In this work, the effect of CuPt
B
ordering
on the optoelectronic
properties of Ga
0.5
In
0.5
P is studied by combining
in situ
transmission electron microscopy measurements and
density functional theory (DFT) calculations. GaInP layers were grown
by metal organic vapor phase epitaxy with a CuPt
B
single-variant-induced
ordering due to the intentional misorientation of the Ge(001) substrate.
Moreover, the degree of order was controlled using Sb as the surfactant
without changing other growth parameters. The presence of antiphase
ordered domain boundaries (APDBs) between the ordered domains is studied
as a function of the order parameter. The
in situ
electrical measurements on a set of samples with controlled degree
of order evidence a clear anisotropic electrical conductivity at the
nanoscale between the [110] and [1–10] orientations, which
is discussed in terms of the presence of APDBs as a function of the
degree of order. Additionally, DFT calculations allow to determine
the differences in the optoelectronic properties of the compound with
and without ordering through the determination of the dielectric function.
Finally, the anisotropy of the electrical conductivity for the ordered
case is also discussed in terms of the effective mass calculated from
the band structure on specific
k
-paths. By comparing
the experimental measurements and the theoretical calculations, two
factors have been presented as the main contributors of the electric
conductivity anisotropy of CuPt
B
-type ordered GaInP thin
films: antiphase boundaries that separate domains with uniform order
(APDBs) and the anisotropy of the effective mass due to the alternating
of In/Ga rich planes.
“…The bimodal feature of the charges of indium atoms is consistent with previous work [50], stemming from different local environments of indium atoms. The enlarged charge transfer in amorphous structures increases the probability of long-distance electromigration under the transient electrical field induced by programming pulses [88], which is detrimental to the cycling endurance of devices [89,90]. For RESET operations, the higher the melting temperature T m , the greater the power consumption.…”
Chalcogenide phase-change materials (PCMs) based random access memory (PCRAM) enter the global memory market as storage-class memory (SCM), holding great promise for future neuro-inspired computing and non-volatile photonic applications. The thermal stability of the amorphous phase of PCMs is a demanding property requiring further improvement. In this work, we focus on indium, an alloying ingredient extensively exploited in PCMs. Starting from the prototype GeTe alloy, we incorporated indium to form three typical compositions along the InTe-GeTe tie line: InGe3Te4, InGeTe2 and In3GeTe4. The evolution of structural details, and the optical properties of the three In-Ge-Te alloys in amorphous and crystalline form, was thoroughly analyzed via ab initio calculations. This study proposes a chemical composition possessing both improved thermal stability and sizable optical contrast for PCM-based non-volatile photonic applications.
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