Hybrid P-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors With Trench and Gate-All-Around Structure

Lin, Yen-Wei; Cheng, Che-Hsiang; Jhan, Yi‐Ruei; Kurniawan, Erry Dwi; Du, Yan-Ting; Lin, Yu-Hsien; Wu, Yung-Chun

doi:10.1109/tnano.2018.2848283

Cited by 8 publications

(3 citation statements)

References 14 publications

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“…To further improve its performance, an Fe-FinFET with a trench structure (trench Fe-FinFET) is proposed in this work. Most FETs with a trench structure produced to date [15][16][17][18] have been designed as junctionless, ultra-thin channel transistors to ensure that the channel is fully depleted and to suppress short channel effects (SCEs). However, this design may result in degraded carrier mobility [19] and lower on current (I ON ).…”

Section: Introductionmentioning

confidence: 99%

Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application

Yan

Sun

et al. 2022

Nanomaterials

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Ferroelectric fin field-effect transistors with a trench structure (trench Fe-FinFETs) were fabricated and characterized. The inclusion of the trench structures improved the electrical characteristics of the Fe-FinFETs. Moreover, short channel effects were suppressed by completely surrounding the trench channel with the gate electrodes. Compared with a conventional Fe-FinFET, the fabricated trench Fe-FinFET had a higher on–off current ratio of 4.1 × 107 and a steep minimum subthreshold swing of 35.4 mV/dec in the forward sweep. In addition, the fabricated trench Fe-FinFET had a very low drain-induced barrier lowering value of 4.47 mV/V and immunity to gate-induced drain leakage. Finally, a technology computer-aided design simulation was conducted to verify the experimental results.

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Section: Introductionmentioning

confidence: 99%

Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application

Yan

Sun

et al. 2022

Nanomaterials

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“…The gate-all-around (GAA)-based nanosheets have the strongest gate controllability to lower the leakage current. Also, Junctionless field-effect transistors (JL-FET) with high and uniform doping in channel and source/drain regions have much attraction [5]- [11]. JL-FET can avoid complex source and drain doping engineering, has a low thermal budget for flexible high-k metal gate adoption and it is easily integrated for 3D IC and NAND.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

Tsai

Peng

Sun

et al. 2019

IEEE J. Electron Devices Soc.

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Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more W eff per existing footprint and better parallel resistance, resulting in smaller total resistance. Also, the GAA stacked NS device shows superior electrical properties, including high Ion/Ioff ratio (>10 8), steep subthreshold swing (SS) = 100 mV/dec, very low drain-induced-barrier-lowering (DIBL) = 0.127 mV/V and usually off at Vg = 0 V, owing to superior gate controllability. More, the 3D TCAD simulation has applied for analysis of physical characteristics of the proposed devices. INDEX TERMS Gate all around, junctionless, nanosheet, multi gate, stacked FET.

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“…An ultra-thin body (UTB) structure and hybrid channel enable full depletion at the off state. [11][12][13][14] Moreover, the hybrid channel JL-FET, with an N channel and P-type substrate, is shown to be superior to SCE. [15][16][17][18][19][20][21] This study discusses the effects of the shell N/P hybrid channel JL-FET NW structure and planar structure.…”

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confidence: 99%

Hybrid N-Type Poly-Si Ultra-Thin Nanowire Shell Channel with P-Substrate Structure by Electron Beam Lithography Adjustment for Junctionless Field-Effect Transistors

Tsai¹,

Chiang²,

Lin³

et al. 2018

ECS J. Solid State Sci. Technol.

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This study proposes a new hybrid N channel/P substrate for junctionless field-effect transistors (JL-FET) by using electron beam lithography adjustment for the shell structure. The nanowire (NW) shell JL-FET exhibits the superior electrical properties, including high ON/OFF current ratio of 6 × 10 6 , low subthreshold swing (SS) of 95 mV/decade and drain-induced barrier lowering value (DIBL) of 50 mV/V. This NW shell structure JL-FET is simple to fabricate, and highly favorable for use in advanced System-on-panel (SoP) and three-dimensional (3-D) stacked IC applications.

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Hybrid P-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors With Trench and Gate-All-Around Structure

Cited by 8 publications

References 14 publications

Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application

Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application

Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

Hybrid N-Type Poly-Si Ultra-Thin Nanowire Shell Channel with P-Substrate Structure by Electron Beam Lithography Adjustment for Junctionless Field-Effect Transistors

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