Hole confinement MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructures

Design and optimization of a buried channel PMOS integrable in a Si1−xGex BiCMOS process

“…This is because as the gate voltage becomes negative, initially inversion occurs in the buried SiGe channel, and the capacitance is [10,30,35]. Here it indicates that the band offsets have been simulated correctly in device simulation.…”

Determination of Band Discontinuities in Silicon Heterostructures

“…The saturation of the SiGe channel hole density can be explained as follows; once a large number of holes flows in the silicon cap layer, the charge screens the gate potential and fewer holes are added to the SiGe channel with the increasing gate voltage, limiting the maximum concentration of high mobility holes[39]. In the present case, gate bias beyond VG = -2 25.…”

SiGe band engineering for MOS, CMOS and quantum effect devices

“…In their experiments, Nayak et al extracted the room temperature hole mobility based on a long channel device. The mobility, as obtained from the slope of the saturation transconductance versus gate voltage, of the buried SiGe channel device was 155 cm2/V-s while the bulk-Si control device yielded a mobility of 122 cmZ/V-s. Reported room temperature hole mobility enhancement using the gated SiGe structure has varied from about 30% to 70% (depending upon Ge mole fraction) over its Si counterpart [12,28,29,30]. Additional improvement in channel mobility has been observed in SiGe p-MOS devices built on SOI.…”