The properties of a highly selective chemical etchant composed of hydrofluoric acid, hydrogen peroxide, and acetic acid (HF:H202:CH3COOH) is investigated in etching SiGe/Si heterostructures. This solution has been found to etch Si~_= Ge~ much faster than Si over the entire range of Ge contents. The etch rate dependences are presented as functions of solution composition, Ge content, dopant type, diluent type, temperature, and stirring. Both n-type and p-type Si~ =Ge= layers with Ge contents of 0 -< x -< 0.60 and 0 ~ x <-1.00, respectively, are investigated. It is found that the n-type samples etch at a faster rate than p-type for all Ge contents examined. When CH3COOH is used as the diluent instead of H20 a significant enhancement in the etch rate results for all concentrations of Ge studied. Also, the amount of H202 in the presence of CH3COOH has a significant effect on the magnitude of the etch rate as well as its behavior over time.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 169.230.243.252 Downloaded on 2014-11-26 to IP
Ge0.5Si0.5 strained-layer pin photodiodes, in which multiple strained layers serve as the absorption region, have been fabricated. These devices exhibit an optical response at wavelengths beyond 1.3 μm at normal incidence. The measured external quantum efficiencies at an applied bias of 4 V are 17% at 0.85 μm and 1% at 1.3 μm, respectively. Excellent electrical characteristics evidenced by the avalanche breakdown at 20 V have also been demonstrated.
In this paper, we review recent progress in SiGe MOS technology. Progress in high mobility p-channel and n-channel devices will be presented as well as some of the materials and processing issues related to the fabrication of these heterostructures. In addition, we will present an outlook on the integration of these devices to complimentary MOS (CMOS) based on Si on Insulator technology (SOl). New directions of novel devices utilizing selective epitaxial growth and the integration of Si/Ge superlattices for enhanced performance in field effect transistors are described. Finally, we will examine some of the materials challenges of integrating SiGe technologies with current CMOS production processes.
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