2015
DOI: 10.1007/s11664-015-3949-4
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High-Temperature (1200–1400°C) Dry Oxidation of 3C-SiC on Silicon

Abstract: In a novel approach, high temperatures (1200-1400°C) were used to oxidize cubic silicon carbide (3C-SiC) grown on silicon substrate. High-temperature oxidation does not significantly affect 3C-SiC doping concentration, 3C-SiC structural composition, or the final morphology of the SiO 2 layer, which remains unaffected even at 1400°C (the melting point of silicon is 1414°C). Metal-oxide-semiconductor capacitors (MOS-C) and lateral channel metaloxide-semiconductor field-effect-transistors (MOSFET) were fabricated… Show more

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Cited by 16 publications
(20 citation statements)
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“…In the last ten years, there have been many improvements in 3C-SiC substrate preparation [18][19][20][21][22][23][24] that a defect density below 400 cm -1 became possible [24]. There were also further developments in 3C-SiC device processing, including implantation [25,26], oxidation [27][28][29], and metallisation [30,31]. 600 V vertical power MOSFET was demonstrated with a specific on-resistance of 8.2 mΩ.cm 2 [32].…”
Section: Introductionmentioning
confidence: 99%
“…In the last ten years, there have been many improvements in 3C-SiC substrate preparation [18][19][20][21][22][23][24] that a defect density below 400 cm -1 became possible [24]. There were also further developments in 3C-SiC device processing, including implantation [25,26], oxidation [27][28][29], and metallisation [30,31]. 600 V vertical power MOSFET was demonstrated with a specific on-resistance of 8.2 mΩ.cm 2 [32].…”
Section: Introductionmentioning
confidence: 99%
“…We can see with the increase of temperature from 1200 to 1500°C that D it reduces from 2 × 10 12 to 5 × 10 11 cm Figure 15(b) shows the linear transfer characteristics and field-effect mobilities of the devices measured at room temperature [36]. The V T values for the devices without any passivation are typically around 5 [3,49] which is due to the large number of traps at the interface. The net charge of these traps is negative in nature.…”
Section: High-temperature Oxidationmentioning
confidence: 95%
“…The area under the conductance peak is a measure for D it . The position of the peak corresponds to the energy position in the band gap and as all these peaks occur at gate bias close to V FB , it can be inferred that these peaks are a measure of D it close to the CB edge of 3C-SiC [49]. Devices without the N 2 O post-oxidation annealing have larger area under G-V curves when compared with the annealed device, implying higher D it for non-annealed devices.…”
Section: High-temperature Dry/thermal Oxidation (1200-1400°c) and N 2mentioning
confidence: 95%
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“…The oxide layer thickness increased slowly below 1200 o C and rapidly when the temperatures are higher than 1500 o C [11] . This term oxidation process can use as film growth on SiC surface that applicable in electronic devices [12] .…”
Section: Introductionmentioning
confidence: 99%