High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

“…15a-c, respectively. It is assumed that the process integration of each generation is based on that of Toshiba's CMOS platform; CMOS5 [20], CMOS6 [21], and CMOS7. It is important to note that the thickness of the gate oxide, the silicon, and the buried oxide must be shrunk in order to keep the signal constant as the operation voltage is reduced.…”

Full-chip leakage analysis for 65 nm CMOS technology and beyond

“…Bitline leakage from unaccessed cells in SRAM bitlines has been recognized as the major cause of read failure in low voltage SRAMs [6]. Fig.…”

“…For the success of the aggressive scaling, it is indispensable to implement MOSFET performance booster techniques such as high stress contact-etch-stop-layer and eSiGe [6]. However, these boosters also have an impact on leakage current, which is not covered in most of the previous publications.…”

“…Moreover, in many works (e.g., [4,7]), leakage analysis is often performed on a single MOSFET. Nevertheless, actual layouts usually have stacked gate MOSFETs deployed in critical paths [6].…”

Maxwell Fisheye Lens as a Waveguide Crossing for Integrated Photonics

“…To accomodate this increase in density, lithographic manufacturing tool costs escalated from $10,000 to $35 million, contributing to the $300 billion industry worldwide 2 . This has increased the cost per transistor several orders of magnitude 3,4 .…”