Full-chip leakage analysis for 65 nm CMOS technology and beyond

Xue, Jiying; Li, Tao; Deng, Yangdong

doi:10.1016/j.vlsi.2010.05.002

Cited by 14 publications

(7 citation statements)

References 27 publications

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“…The proposed method is tested in 65 nm chips and found to be very effective. 3 Leakage power has turn out to be a significant problem in submicron range devices. The choice of leakage lessening technique turn out to be best when the circuit designer chooses it.…”

Section: Literature Survey On Leakage Reduction Techniquesmentioning

confidence: 99%

Novel 10-T Write Driver SRAM Design Using 45 nm CMOS Technology with Leakage Current Reduction Scheme for FPGA Routing Switch Architecture

Narayanan¹,

Korah²,

Swarnalatha³

2018

Journal of Nanoelectronics and Optoelectronics

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Bulk Complementary metal oxide semiconductor (CMOS) technology suffers from severe leakage power for gate lengths lesser than 45 nm. Static Random access memory (SRAMs) occupy a significant space in the memory architecture of system on chip (SOCs). To reduce the adverse effects of CMOS technology, SRAMs are implemented using FinFet technology. This research presents a new leakage reduction technique for SRAM cell implemented in FinFet technology. The proposed technique is a combined implementation of diode connected load transistors which operate only in saturation when turned on, to cutoff leakage current through access transistors and sleep transistors to control the flow of leakage current through the SRAM cell. The combined effect of these two types of transistors reduces leakage current in the range of nanoamperes. Moreover, the above stated technique when implemented in Fin Field Effect transistor (FinFet) SRAM structures becomes much suitable for memory architectures. Routing is an important step in Field programmable gate array (FPGA) design which is totally in view of how the interconnection is finished amid of the Configurable logic blocks (CLBs). In order to reduce the power consumption as well as power dissipation of the FPGA routing circuit, Different transistor styles of FinFet SRAM such as 6T and 10T structures are combined with Type-II write driver structure and it is simulated using Tanner (T-Spice) with 45 nm technology. Results show significant reduction in static current and power dissipation. With reasonable read/write stability in standby Type with a slight increase in area.

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Section: Literature Survey On Leakage Reduction Techniquesmentioning

confidence: 99%

Novel 10-T Write Driver SRAM Design Using 45 nm CMOS Technology with Leakage Current Reduction Scheme for FPGA Routing Switch Architecture

Narayanan¹,

Korah²,

Swarnalatha³

2018

Journal of Nanoelectronics and Optoelectronics

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“…Table 5 presents the power-delay product (PDP) results of the CMOS logic gates at different technology nodes. When we are moving towards the nanoscale dimensions, the power dissipation and propagation delay both are increased (Dennard et al, 2007;Xue et al, 2010). Propagation delay is inversely proportional to the trans-conductance of the relative transistor therefore with reducing in technology the propagation delay is increased.…”

Section: Power Dissipationmentioning

confidence: 99%

“…Figure 1 indicates the importance of leakage current with reducing the physical gate length of the MOS transistor. This graph shows the leakage power dissipation has been growing at a considerably faster pace as technology scaled down (Dhar, Pattanaik, & Rajaram, 2012;Xue, Li, Deng, & Yu, 2010).…”

Section: Introductionmentioning

confidence: 99%

ONOFIC approach: low power high speed nanoscale VLSI circuits design

Sharma

Pattanaik

Raj

2013

International Journal of Electronics

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Shrinking in the device dimensions increases the device density on the chip and thus reducing the overall chip area requirement for logic implementation. Minimising the chip area is not a lonely optimisation performance factor for a VLSI chip designer. The other equally important performance parameters such that power dissipation and propagation delay are the thinkable facts for a designer. The focusable part of power dissipation is the huge leakage current in deep submicron (DSM) regime. Many leakage reduction techniques are applied to reduce the leakage current in the DSM regime but they have own limitations. Our proposed on/off logic (ONOFIC) approach gives an excellent settlement between power dissipation and propagation delay for designing the nanoscale CMOS circuits. It uses extra insertion of two transistors (an NMOS and a PMOS) within the logic block. The exact on/off level of the ONOFIC block improves the power dissipation and propagation delay of the logic circuits. In this article, ONOFIC approach is compared with the LECTOR leakage reduction technique and output results show that our proposed approach significantly reduces the power dissipation and enhancing the speed of the logic circuits with superior power-delay product.

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“…Notably, the state variables are often realized by (i) leaky voltage integrators using a standalone capacitor or the gate capacitor of a transistor (switched-capacitor integrators) 17 , 25 , 26 , (ii) current-starved inverter 27 , and (iii) operational transconductance amplifier (OTA)-based integrator 19 , 28 . Scaling down a metal-oxide-semiconductor field-effect transistor (MOSFET) in the integrator (particularly channel length below 100 nm) causes a significant rise in subthreshold leakage current 29 – 31 , and thus a large decrease in the relaxation time of the integrator with a given capacitor. For temporal learning, the relaxation time is a priori preferred to be comparable to that of the biological counterpart in favor of energy-efficient learning, sacrificing unnecessarily fast response.…”

Section: Introductionmentioning

confidence: 99%

Scalable excitatory synaptic circuit design using floating gate based leaky integrators

Kornijcuk

Lim

Kim

et al. 2017

Sci Rep

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We propose a scalable synaptic circuit realizing spike timing dependent plasticity (STDP)—compatible with randomly spiking neurons. The feasible working of the circuit was examined by circuit simulation using the BSIM 4.6.0 model. A distinguishable feature of the circuit is the use of floating-gate integrators that provide the compact implementation of biologically plausible relaxation time scale. This relaxation occurs on the basis of charge tunneling that mainly relies upon area-independent tunnel barrier properties (e.g. barrier width and height) rather than capacitance. The circuit simulations feature (i) weight-dependent STDP that spontaneously limits the synaptic weight growth, (ii) competitive synaptic adaptation within both unsupervised and supervised frameworks with randomly spiking neurons. The estimated power consumption is merely 34 pW, perhaps meeting one of the most crucial principles (power-efficiency) of neuromorphic engineering. Finally, a means of fine-tuning the STDP behavior is provided.

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Full-chip leakage analysis for 65 nm CMOS technology and beyond

Cited by 14 publications

References 27 publications

Novel 10-T Write Driver SRAM Design Using 45 nm CMOS Technology with Leakage Current Reduction Scheme for FPGA Routing Switch Architecture

Novel 10-T Write Driver SRAM Design Using 45 nm CMOS Technology with Leakage Current Reduction Scheme for FPGA Routing Switch Architecture

ONOFIC approach: low power high speed nanoscale VLSI circuits design

Scalable excitatory synaptic circuit design using floating gate based leaky integrators

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