Novel 10-T Write Driver SRAM Design Using 45 nm CMOS Technology with Leakage Current Reduction Scheme for FPGA Routing Switch Architecture

Abstract

Bulk Complementary metal oxide semiconductor (CMOS) technology suffers from severe leakage power for gate lengths lesser than 45 nm. Static Random access memory (SRAMs) occupy a significant space in the memory architecture of system on chip (SOCs). To reduce the adverse effects of CMOS technology, SRAMs are implemented using FinFet technology. This research presents a new leakage reduction technique for SRAM cell implemented in FinFet technology. The proposed technique is a combined implementation of diode connected load transistors which operate only in saturation when turned on, to cutoff leakage current through access transistors and sleep transistors to control the flow of leakage current through the SRAM cell. The combined effect of these two types of transistors reduces leakage current in the range of nanoamperes. Moreover, the above stated technique when implemented in Fin Field Effect transistor (FinFet) SRAM structures becomes much suitable for memory architectures. Routing is an important step in Field programmable gate array (FPGA) design which is totally in view of how the interconnection is finished amid of the Configurable logic blocks (CLBs). In order to reduce the power consumption as well as power dissipation of the FPGA routing circuit, Different transistor styles of FinFet SRAM such as 6T and 10T structures are combined with Type-II write driver structure and it is simulated using Tanner (T-Spice) with 45 nm technology. Results show significant reduction in static current and power dissipation. With reasonable read/write stability in standby Type with a slight increase in area.