High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

Wu, Chau-Neng; Lin, D.; Keshavarzi, Ali; Huang, Chihpin; Chan, Chuan-Tsung; Tseng, Chien-Chou; Chen, C.L.; Hsieh, Chih-Hua; Wong, Kwok Yin; Cheng, Mu Jeng; Li, T.H.; Lin, Yen-Sheng; Yang, L.; Lin, Chih-Yang; Hou, Chin-Shan; Lin, Hang-Chun; Yang, J.L.; Yu, K.F.; Chen, M.J.; Hsieh, T.H.; Peng, Yarui; Chou, Ching-Chuan; Lee, C.J.; Huang, Chenghao; Lu, Chih‐Yuan; Yang, Fu-Liang; Chen, H.K.; Weng, Lei-Wen; Yen, Po-Wen; Wang, S.H.; Chang, Stock; Chuang, Sheng-Ming; Gan, Tian-Choy; Wu, Tian-Li; Lee, T.Y.; Huang, Wen-Tsung; Huang, Yeh-Jen; Tseng, Yuan‐Chieh; Wu, CH; Ouyang, Eric; Hsu, Keh‐Ying; Lin, Lang; Wang, S.B.; Kwok, T.; Su, Chang; Tsai, Chung-Hung; Huang, Michael; Lin, Horng–Chih; Chang, A.; Liao, Si-Yu; Chen, L.S.; Chen, J.H.; Lim, Poon Nian; Yu, Xin; Ku, S.Y.; Lee, Y.B.; Hsieh, Peter; Wang, P.W.; Chiu, Yi-Hung; Lin, Shy-Jay; Tao, Hun-Jan; Cao, Min; Mii, Y. J.

doi:10.1109/iedm.2010.5703430

Cited by 71 publications

(35 citation statements)

References 1 publication

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“…Pseudo-random sequence with equal probability of all transitions (data Impact of Technology Scaling on the Minimum Energy Point for FinFET Based Flip-Flops activity rate 0.5) is considered in power consumption calculation to reflect average internal power consumption given the uniform data distribution. PTM-MG used the published results from foundries such as Intel, TSMC, and IBM [16][17][18][19] to extract the fitting PTM parameters such as DIBL, sub-threshold slope by fine-tuning both primary parameters (Gate length, Fin thickness, Fin height, and Fin pitch) and secondary parameters (Gate work function, channel doping, source-drain channel coupling, and DIBL coefficient) [11] to match on-current and offcurrent of the published results.…”

Section: Simulation Setupmentioning

confidence: 99%

Impact of technology scaling on the minimum energy point for FinFET based flip-flops

Abdelkader

Mostafa

Abdelhamid

et al. 2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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Analysis of FinFET based transmission gate (TG), sense amplifier (SA), and semi dynamic (SD) Flip-flops metrics are evaluated with technology scaling from 20nm down to 7nm technology node. The impact of supply voltage variation on delay, power, and energy is reported. The power delay product of Flip-flops is enhanced with technology scaling. The optimum supply voltage value at each technology node from minimum energy perspective is evaluated which is used by the industry to optimize logic and memory circuitry designs. For instance, considering the 7nm TG Flip-flop, the optimum supply voltage from energy saving point of view occurs at 0.65V. The work also characterizes each Flip-flop according to the obtained simulation results. SD Flip-flop has the best performance, however it exhibits high power consumption. TG Flip-flop is the best choice from power dissipation perspective, but it has high clock load. SA Flip-flop has a very useful feature of monotonous transitions at the outputs, which drives fast domino logic, however it might have glitches and it is the most vulnerable to soft errors.

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Section: Simulation Setupmentioning

confidence: 99%

Impact of technology scaling on the minimum energy point for FinFET based flip-flops

Abdelkader

Mostafa

Abdelhamid

et al. 2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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“…In order to achieve better electrostatic control and reduce short channel effects, FinFETs have been successfully used for the 22-nm technology node [5]. To achieve an even better electrostatic control [6], vertically-stacked Silicon NanoWire FETs (SiNWFETs) with gate-all-around control have shown to be a natural extension of FinFETs.…”

Section: Introductionmentioning

confidence: 99%

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs

Zhang

Gaillardon

Micheli

2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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Abstract-We extend ambipolar silicon nanowire transistors by using three independent gates and show an efficient approach to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying different bias patterns to the three gates. Uncommitted logic gates can thus be configured to implement different logic functions for dual-threshold-voltage design using a wiring scheme, to target either high-performance or low-leakage applications. Synthesis of benchmark circuits with these devices shows comparable performance and 54% reduction of leakage power consumption compared to FinFET technology.

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“…Numerous enabling approaches such as high-κ/metal gate [2,3] and FinFET [4,5] have been used. Since the dynamic power dissipation of CMOS logic is proportional to the square of supply voltage VDD, VDD scaling provides a way to constrain power dissipation of integrated circuits (ICs).…”

Section: Digital Circuitsmentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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Abstract:In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

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High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

Cited by 71 publications

References 1 publication

Impact of technology scaling on the minimum energy point for FinFET based flip-flops

Impact of technology scaling on the minimum energy point for FinFET based flip-flops

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

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