Hardware optimization for a reconfigurable Polyphase-FFT design using common sub-expression elimination

Abstract

In this paper, the implementation of a reconfigurable Polyphase-FFT circuit and its building blocks designed for low hardware complexity are presented. The Polyphase-FFT circuit can be configured to support 8, 16 or 32 channels where each FIR filter in the Polyphase filter can be configured to have up to 15 taps. The Common SubExpression Elimination algorithm (CSE) has been used to reduce the number of partial products for multiplication operations in FIR filter, phase shifter, and FFT circuits. Real and complex multiplications in these building blocks have been transformed into sums of two products (STP) with view to detecting and eliminating digits shared by both terms. Circuit analysis has shown that a significant reduction in logic resources is achieved using this technique. Simulation results for the CSE-based reconfigurable Polyphase-FFT circuit and its building blocks are presented and compared with conventional realizations.

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

“…For designs involving variable multiplication and incorporating generic multipliers, it has been demonstrated that a design approach combining bit-slice arithmetic and the CSE optimization technique can result in significant hardware savings [24]. Using bit-slice arithmetic, the multiplier operand is decomposed into multiple signals and common digits among a group of two or more signals are identified.…”

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

“…The arithmetic configuration required to compute a partial sum of complex products can be mapped on a single PE cell. Circuit implementations based on a combination of common subexpression and bitslice arithmetic (CSE-BitSlice) techniques have also been incorporated in the PE design to achieve low-complexity and high-throughput performance [30].…”