Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

Abstract

A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSEBitSlice) arithmetic for hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The CSEBitSlice technique has been applied to the design and implementation of 12×12 and 42×42 bit real multipliers, a complex multiplier, a 6-tap FIR filter, and a 5-point DFT circuit. For comparison purposes, circuit implementations of the same arithmetic and DSP functions have been carried out using Radix-4 Booth and CSA algorithms. Simulation results based on implementations using the Xilinx FPGA 5VLX330FF1760-2 device shows that the circuits based on the CSE-BitSlice techniques require fewer logic resources and yield higher throughput as compared to the CSA and Radix-4 Booth based circuits.

Frequent Statement and Dereference Elimination for Imperative and Object-Oriented Distributed Programs

“…The techniques of common subexpression elimination (CSE) [ 8 , 9 ] are closed to our work. In [ 10 ], a type system for CSE of the while language is introduced.…”