Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m)

Ho, H. L.

doi:10.1007/s11265-013-0791-x

Cited by 5 publications

(1 citation statement)

References 8 publications

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“…Various types of architectures have been proposed in the literature for PB multiplication, such as bit‐serial , bit‐parallel , digit‐serial , systolic , semi‐systolic , sequential , and pipelined . Each type of architecture has its advantages and shortcomings.…”

Section: Introductionmentioning

confidence: 99%

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2^m ) for Irreducible Polynomials

Mathe¹,

Boppana²

2017

ETRI Journal

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Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and fieldprogrammable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.

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Section: Introductionmentioning

confidence: 99%

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2^m ) for Irreducible Polynomials

Mathe¹,

Boppana²

2017

ETRI Journal

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An area-efficient bit-serial sequential polynomial basis finite field GF(2 ) multiplier

Pillutla

Boppana

2020

AEU - International Journal of Electronics and Communications

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New polynomial basis versatile multiplier over GF(2<sup>m</sup>) for low-power on-chip crypto-systems

Khairallah

Ghoneima

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m)

Cited by 5 publications

References 8 publications

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2^m ) for Irreducible Polynomials

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2^m ) for Irreducible Polynomials

An area-efficient bit-serial sequential polynomial basis finite field GF(2 ) multiplier

New polynomial basis versatile multiplier over GF(2<sup>m</sup>) for low-power on-chip crypto-systems

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Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m)

Cited by 5 publications

References 8 publications

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2 m ) for Irreducible Polynomials

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2 m ) for Irreducible Polynomials

An area-efficient bit-serial sequential polynomial basis finite field GF(2 ) multiplier

New polynomial basis versatile multiplier over GF(2<sup>m</sup>) for low-power on-chip crypto-systems

Contact Info

Product

Resources

About

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2^m ) for Irreducible Polynomials

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2^m ) for Irreducible Polynomials