Design and implementation of a Multiplierless Reconfigurable DFT/DCT processor

Ho, H. L.; Szwarc, V.; Kwaśniewski, T.

doi:10.1109/newcas.2009.5290428

Cited by 2 publications

(3 citation statements)

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“…Compared to the non-optimized case the maximum number of real additions required by the modified equation (8) has been reduced. The algorithm to identify and eliminate common patterns for the expression depicted in (5) Digital communication circuits frequently require both real and complex multipliers.…”

Section: Common Sub-expression Eliminationmentioning

confidence: 99%

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Hardware optimization for a reconfigurable Polyphase-FFT design using common sub-expression elimination

Szwarc

Kwaśniewski

2007

2007 50th Midwest Symposium on Circuits and Systems

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In this paper, the implementation of a reconfigurable Polyphase-FFT circuit and its building blocks designed for low hardware complexity are presented. The Polyphase-FFT circuit can be configured to support 8, 16 or 32 channels where each FIR filter in the Polyphase filter can be configured to have up to 15 taps. The Common SubExpression Elimination algorithm (CSE) has been used to reduce the number of partial products for multiplication operations in FIR filter, phase shifter, and FFT circuits. Real and complex multiplications in these building blocks have been transformed into sums of two products (STP) with view to detecting and eliminating digits shared by both terms. Circuit analysis has shown that a significant reduction in logic resources is achieved using this technique. Simulation results for the CSE-based reconfigurable Polyphase-FFT circuit and its building blocks are presented and compared with conventional realizations.

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Section: Common Sub-expression Eliminationmentioning

confidence: 99%

“…The Polyphase-FFT circuit presented here supports multiplexing/demultiplexing operations on a group of FDM signals consisting of 8, 16 or 32 channels [7][8].…”

Section: Introductionmentioning

confidence: 99%

Hardware optimization for a reconfigurable Polyphase-FFT design using common sub-expression elimination

Szwarc

Kwaśniewski

2007

2007 50th Midwest Symposium on Circuits and Systems

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“…Hence a unified or reconfigurable architecture which can perform multiple transforms as per the requirement is desirable for such applications. There are few proposals in literature developing unified/reconfigurable architectures for multiple transforms like DFT or DCT [10,11,12].…”

Section: Introductionmentioning

confidence: 99%

Systolic architecture implementation of 1D DFT and 1D DCT

Mamatha

Raj

Tripathi

et al. 2015

2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES)

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Discrete Fourier Transform is widely used in signal processing for spectral analysis, filtering, image enhancement , OFDM etc.. Cyclic convolution based approach is one of the techniques used for computing DFT. Using this approach an N point DFT can be computed using four pairs of [(M-1)/2]-point cyclic convolution where M is an odd number and N=4M. This work proposes an architecture for convolution based DFT and its FPGA implementation. Proposed architecture comprises of a pre-processing element, systolic array and a post processing stage. Processing element of systolic array uses a tag bit to decide on the type of operation (addition/subtraction) on the input signals. Proposed architecture is simulated for 28 point DFT using ModelSim 6.5 and synthesized using Xilinx ISE10.1 using Vertex 5 xc5vfx100t-3ff1738 FPGA as the target device and can operate at a maximum frequency of 224.9MHz. The performance analysis is carried out in terms of hardware utilization and computation time and compared with existing similar architectures. Further, as the convolution based DCT has two systolic arrays similar to that of DFT , a unified architecture is proposed for 1D DFT/1D DCT.

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Design and implementation of a Multiplierless Reconfigurable DFT/DCT processor

Cited by 2 publications

References 10 publications

Hardware optimization for a reconfigurable Polyphase-FFT design using common sub-expression elimination

Hardware optimization for a reconfigurable Polyphase-FFT design using common sub-expression elimination

Systolic architecture implementation of 1D DFT and 1D DCT

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