A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

Abstract

A reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless and multirate applications is presented. The RSA consists of coarse-grained processing elements that can be configured as complex DSP functions that are the basic building blocks of Polyphase-FIR filters, phase shifters, DFTs, and Polyphase-DFT circuits. The homogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE) cell is connected to its nearest neighbors via configurable switch (SW) elements, enables array expansion for parallel processing and facilitates time sharing computation of high-throughput data by individual PEs. For DFT circuit configurations, an algorithmic optimization technique has been employed to reduce the overall number of vector-matrix products to be mapped on the RSA. The hardware complexity and throughput of the RSA-based DFT structures have been evaluated and compared against several conventional modular FFT realizations. Designs and circuit implementations of the PE cell and several RSAs configured as DFT and Polyphase filter circuits are also presented. The RSA architecture offers significant flexibility and computational capacity for applications that require real time reconfiguration and high-density computing.

Folding Memory Shared Processor Array (FMSPA) Architecture for Channel Estimation of Downlink OFDMA IEEE 802.16e System

“…However this minimum-area solution can not meet the low latency requirement of mobile WiMAX OFDMA system. Fast but large matrix vector multiplication architecture, i.e Systolic array architecture [10,11,12,13 ] has advantages in regularity and high throughput but still suffers the overlapping data storages, idle processing and high area requirement. MSPA (Memory Sharing Processor Array) [9] overcomes these problems by minimize the data storage by sharing memory units to several processor array and achieve better efficiency than conventional systolic architecture, but the data throughput is not suitable and far beyond the clock alocation compute based on standard parameter i.e sample period is much larger than the computational delay of MSPA hardware unit.…”