Pipelined FFT architectures: A review

Singh, Sharad; Kedia, Jyoti

doi:10.1109/eesco.2015.7253865

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Flexible Radix-2/4/8 Mixed Butterfly Unit1

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2016

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“…While the higher radix algorithm reduces the computing stages, it also requires more adders and multipliers compared to radix-2 or radix-4 butterfly units [4,15]. The increasing utilization of float point units (FPUs) in a complete higher radix butterfly unit (BU) significantly limits the practicability of higher radix algorithm in VLSI design.…”

Section: Flexible Radix-2/4/8 Mixed Butterfly Unitmentioning

confidence: 99%

An ultra-long FFT architecture implemented in a reconfigurable application specified processor

Feng

Wang

et al. 2016

IEICE Electron. Express

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This paper presents an efficient architecture for performing 128 points to 1M points Fast Fourier Transformation (FFT) based on mixed radix-2/4/8 butterfly unit. The proposed FFT architecture reduces the computation cost by taking the advantage of the radix-8 FFT algorithm while remaining compatible with sequences whose data length is an integral power of 2. Further optimizations for reconfigurable application specified processor are developed. First, we propose a separated radix-2/4/8 butterfly unit which is more flexible than an entire radix-2/4/8 butterfly unit; second, for the sequences longer than 256K points, an efficient 2-epoch FFT solution is realized. This FFT architecture is implemented in a reconfigurable application specified processor. The computation time of our architecture is 676 us and 14.8 ms for 128K and 1M points FFTs respectively.

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Section: Flexible Radix-2/4/8 Mixed Butterfly Unitmentioning

confidence: 99%