Half-Select-Free Low-Power Dynamic Loop-Cutting Write Assist SRAM Cell for Space Applications

Pal, Soumitra; Bose, Subhankar; Ki, Wing-Hung; Islam, Aminul

doi:10.1109/ted.2019.2952397

Cited by 49 publications

(50 citation statements)

References 30 publications

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“…This overlooks the RSNM, WSNM, and P L variability. A new performance metric has been proposed in Pal et al, 26 which is called reliability EQM (REQM). This does not take into account the T RA , T WA , and P L variability.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

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Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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Summary This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

“…Then, this cell laches the initial value of Q / QB node. As a result, the proposed SEHF11T call has capable of bit‐interleaving architecture, and consequently, various ECCs can be applied to mitigate soft‐error, being in forms of single‐cell upsets (SCUs) and multiple‐cell upsets (MCUs) 26 …”

Section: Proposed 11t Sram Cellmentioning

confidence: 99%

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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“…Many SRAM bit-cell design [ 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 ] have been presented to enhance circuit stability for robust low voltage/power operation. In [ 9 , 10 , 11 , 12 , 13 , 14 , 15 ], are provided stacked transistors to solve the problem of half-selected read error, but they bring worse write capacity. In order to overcome this problem, a word line boost circuit technology to improve the write capability are presented in [ 16 , 17 ].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, these designs need additional write assist techniques to improve write margin [ 18 , 19 ]. Another solution is to cut off the cross-coupled inverter’s feedback path to improve the write capability, but the half-selected write stability still affected [ 12 , 13 ]. In [ 21 ], uses a single-ended write structure to reduce circuit complexity, but each column needs to use an extra read feedback circuit to enable it to operate stably in the subthreshold region, but the number of transistors will still be as high as 12.…”

Section: Introductionmentioning

confidence: 99%

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications

Sheu

Tsai

et al. 2021

Sensors

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An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.

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“…2 Since lightweight satellites have limited resources, they require high-density memory cells, and static random-access memory (SRAM) cells are the best alternative for space applications because of their high packing density and improved logic performance. 1 Space presents extreme conditions, like temperature fluctuations and radiation. Due to the weak geomagnetic field in space, radiation and energized particles increase.…”

mentioning

confidence: 99%

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Pal

Divya

et al. 2021

Circuit Theory & Apps

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In advanced technology, static random-access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high-energy particle strikes, which cause soft-error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation-hardened readdecoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read-decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02Â/1.06Â/1.07Â/1.08Â over NS10T/RHD12T/PS10T/RHBD10T at V DD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single-event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. K E Y W O R D Sdigital circuit, low power design, memory design, read stability, SRAM | INTRODUCTIONSatellites have become an integral part of human society, as we rely on satellite communication for a wide range of services, from meteorology to disaster monitoring, from navigation systems to military operations, and so on. 1 As the technology is advancing, lightweight satellites are replacing heavyweight satellites because of their higher manufacturing cost. 2 Since lightweight satellites have limited resources, they require high-density memory cells, and static random-access memory (SRAM) cells are the best alternative for space applications because of their high packing density and improved logic performance. 1 Space presents extreme conditions, like temperature fluctuations and radiation. Due to the weak geomagnetic field in space, radiation and energized particles increase. To withstand this harsh environment, special electronic components and circuits are used. Once a radiation particle strikes a logic circuit at its sensitive node, it generates electron-hole pairs (Figure 1A). These pairs become separated and accumulate at the sensitive node. 3 The accumulated charge at the sensitive node then generates a transient voltage pulse. If enough charge (i.e., critical charge, Q C ) is

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Half-Select-Free Low-Power Dynamic Loop-Cutting Write Assist SRAM Cell for Space Applications

Cited by 49 publications

References 30 publications

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

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