Guaranteeing the Quality of Services in Networks on Chip

Goossens, Kees; Dielissen, J.; Meerbergen, J. van; Poplavko, Peter; Rădulescu, A.; Rijpkema, Edwin; Waterlander, E.; Wielage, Paul

doi:10.1007/0-306-48727-6_4

Cited by 73 publications

(47 citation statements)

References 33 publications

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“…The AEthereal network-on-chip [6], from NXP, uses a timedivision multiple-access (TDMA) scheme for packets that are subject to guaranteed service constraints. Guaranteedservice packets are sent in fixed-length slots.…”

Section: On-chip Communicationmentioning

confidence: 99%

Temporal isolation on multiprocessing architectures

Bui

Lee

Liu

et al. 2011

Proceedings of the 48th Design Automation Conference

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Multiprocessing architectures provide hardware for executing multiple tasks simultaneously via techniques such as simultaneous multithreading and symmetric multiprocessing. The problem addressed by this paper is that even when tasks that are executing concurrently do not communicate, they may interfere by affecting each other's timing. For cyberphysical system applications, such interference can nullify many of the advantages offered by parallel hardware. In this paper, we argue for temporal semantics in layers of abstraction in computing. This will enable us to achieve temporal isolation on multiprocessing architectures. We discuss techniques at the microarchitecture level, in the memory hierarchy, in on-chip communication, and in the instruction-set architecture that can provide temporal semantics and control over timing.

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Section: On-chip Communicationmentioning

confidence: 99%

Temporal isolation on multiprocessing architectures

Bui

Lee

Liu

et al. 2011

Proceedings of the 48th Design Automation Conference

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“…Regular-topology NoC is proposed as on-chip communication architectures primarily using switching and routing technologies [Benini and De Michelli 2002;Dally and Towles 2001;Goossens et al 2003;Sgroi et al 2001;Hemani and Jantsch 2000]. A two-dimensional (2D) folded torus NoC is proposed in Dally and Towles [2001].…”

Section: Previous Workmentioning

confidence: 99%

“…Kumar et al [2002] presented a design methodology for CLICHÉ NoC. Goossens et al [2003] proposed a methodology to provide guaranteed services in NoCs. Siegmund and Muller [2003] presented a methodology to model and synthesize protocols for NoCs.…”

Section: Previous Workmentioning

confidence: 99%

A design methodology for application-specific networks-on-chip

Jiang

Wolf

Henkel

et al. 2006

ACM Trans. Embed. Comput. Syst.

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With the help of HW/SW codesign, system-on-chip (SoC) can effectively reduce cost, improve reliability, and produce versatile products. The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation subsystem design. While a number of codesign methodologies have been proposed for on-chip computation subsystems, many works are needed for on-chip communication subsystems. This paper proposes application-specific networkson-chip (ASNoC) and its design methodology. ASNoC is used for two high-performance SoC applications. The methodology (1) can automatically generate optimized ASNoC for different applications, (2) can generate a corresponding distributed shared memory along with an ASNoC, (3) can use both recorded and statistical communication traces for cycle-accurate performance analysis, (4) is based on standardized network component library and floorplan to estimate power and area, (5) adapts an industrial-grade network modeling and simulation environment, OPNET, which makes the methodology ready to use, and (6) can be easily integrated into current HW/SW codesign flow. Using the methodology, ASNoC is generated for a H.264 HDTV decoder SoC and Smart Camera SoC. ASNoC and 2D mesh networks-on-chip are compared in performance, power, and area in detail. The comparison results show that ASNoC provide substantial improvements in power, performance, and cost compared to 2D mesh networks-on-chip. In the H.264 HDTV decoder SoC, ASNoC uses 39% less power, 59% less silicon area, 74% less metal area, 63% less switch capacity, and 69% less interconnection capacity to achieve 2X performance compared to 2D mesh networks-on-chip.

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“…This would be possible in a real-time environment where processing time budgets and communication services with bandwidth guarantees are given to jobs. Such services can be offered at a reasonable cost by on-chip router networks through independent point-to-point network connections [7,15]. Packetswitched networks are an attractive way to implement the interconnect between the on-chip processors in case their number is large enough.…”

Section: Inmentioning

confidence: 99%

Task-level timing models for guaranteed performance in multiprocessor networks-on-chip

Poplavko

Basten

Bekooij

et al. 2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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We consider a dynamic application running on a multiprocessor network-on-chip as a set of independent jobs, each job possibly running on multiple processors. To provide guaranteed quality and performance, the scheduling of jobs, jobs themselves and the hardware must be amenable to timing analysis. For a certain class of applications and multiprocessor architectures, we propose exact timing models that effectively co-model both the computation and communication of a job. The models are based on interprocessor communication (IPC) graphs [4]. Our main contribution is a precise model of network-on-chip communication, including buffer models. We use a JPEG-decoder job as an example to demonstrate that our models can be used in practice to derive upper bounds on the job execution time and to reason about optimal buffer sizes.

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Guaranteeing the Quality of Services in Networks on Chip

Cited by 73 publications

References 33 publications

Temporal isolation on multiprocessing architectures

Temporal isolation on multiprocessing architectures

A design methodology for application-specific networks-on-chip

Task-level timing models for guaranteed performance in multiprocessor networks-on-chip

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