Task-level timing models for guaranteed performance in multiprocessor networks-on-chip

Abstract

We consider a dynamic application running on a multiprocessor network-on-chip as a set of independent jobs, each job possibly running on multiple processors. To provide guaranteed quality and performance, the scheduling of jobs, jobs themselves and the hardware must be amenable to timing analysis. For a certain class of applications and multiprocessor architectures, we propose exact timing models that effectively co-model both the computation and communication of a job. The models are based on interprocessor communication (IPC) graphs [4]. Our main contribution is a precise model of network-on-chip communication, including buffer models. We use a JPEG-decoder job as an example to demonstrate that our models can be used in practice to derive upper bounds on the job execution time and to reason about optimal buffer sizes.

Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs

“…Its use has been increasingly considered for designing applications for multi-and many-core processors [26], [27]. A synchronous dataflow application graph is a datadriven network of actors (nodes), where the same behavior repeats in each actor every time it is fired.…”

Dataflow Analysis for Real-Time Embedded Multiprocessor System Design

“…The execution order of actors on the same processor is derived from an offline computed schedule. Similar techniques are applied in (Poplavko, Basten, Bekooij, Meerbergen and Mesman, 2003) for soft realtime jobs. Good results could only be obtained by taking measures to limit the difference between the typical and the worst-case response times of the actors.…”

“…These connections can be modeled together with the actors of a job in one SDF graph (Poplavko et al, 2003). Given this SDF graph, the guaranteed minimal throughput of a hard real-time job can be determined.…”

Predictable embedding of large data structures in multiprocessor networks-on-chip

“…The result is a combined SDF graph of the application and the architecture with predictable behavior wrt timing, memory usage etc. See [4] for an example of such a flow. The mapping of data structures onto memories is one of the decisions that should be taken into account in this flow.…”

“…An SDF model for the behavior of the CAs is shown in Fig. 2 4 model the fetching of data. These last three actors can be omitted if all data can be prefetched.…”