Temporal isolation on multiprocessing architectures

In this paper, we introduce a Multicore Response Time Analysis (MRTA) framework. This framework is extensible to different multicore architectures, with various types and arrangements of local memory, and different arbitration policies for the common interconnects. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of performance that can be obtained with different hardware configurations. The MRTA framework decouples response time analysis from a reliance on context independent WCET values. Instead, the analysis formulates response times directly from the demands on different hardware resources. A Generic and Compositional ABSTRACTIn this paper, we introduce a Multicore Response Time Analysis (MRTA) framework. This framework is extensible to different multicore architectures, with various types and arrangements of local memory, and different arbitration policies for the common interconnects. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of performance that can be obtained with different hardware configurations. The MRTA framework decouples response time analysis from a reliance on context independent WCET values. Instead, the analysis formulates response times directly from the demands on different hardware resources.

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“…An alternative approach is based on temporal isolation [14]. The idea here is to statically partition the use of shared resources, e.g.…”

Section: Introductionmentioning

confidence: 99%

A generic and compositional framework for multicore response time analysis

Altmeyer

Davis

Indrusiak

et al. 2015

Proceedings of the 23rd International Conference on Real Time and Networks Systems

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“…As timing has never been treated as a basic premise ago [109], it needs to reconsider the role of timing to CPS. Researches already try to redesign the whole system from hardware platforms [110] to operating system [111], from programming models [112] to architectures [25], from time synchronization protocols [26] to communication standards [113][114][115].…”

Section: Vandv On Timing Behaviormentioning

confidence: 99%

“…Moreover there are also lots of explored technologies for building CPS, e.g. precision timed infrastructure [24], temporal isolation [25], precision time protocol [26], hierarchical scheduling, and various of modeling methods. Therefore, CPS has been applied in different areas: e.g.…”

Section: Introductionmentioning

confidence: 99%

A Comprehensive Technological Survey on Dependable Self-Managing CPS: The Decade of Researches on Correctness and Dependability

Zhou¹,

Hou²,

Zhang³

et al. 2017

Preprint

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Though Cyber Physical Systems (CPS) become very popular in last the decade, dependability of CPS is still a critical issue and related survey is rare. We try to spell out the jigsaw of technologies and figure out the technical trends of dependable self-managing CPS. This survey first recalls the motivation and the similar concepts. By analyzing four generic architectures, we summarize the common characteristics and related assurance technologies, and propose a more generic environment-in-loop processing flow of CPS and a formal interaction flow between physical space and cyber space. Further, the similarity between correctness and dependability is formally analyzed and the new five research questions of dependable self-managing CPS are presented. Then we review the critical technologies and related correctness verification & validation (V&V) methods, the architectures for dependable self-managing CPS. Further, the detail dependability management and V&V technologies are surveyed, which covers the areas of running-time fault management methods and whole life cycle V&V technologies, maintenance and available tool sets. For holistic CPS development, Modeling techniques and MDE (model driven engineering) based V&V methods are analyzed in detail. Then we complete the jigsaw of technologies and figure out the missing part. Further, we propose the technical challenges and the further direction. To our best knowledge, this is the first comprehensive survey on dependable self-managing CPS development and evaluation.

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“…An alternative approach is based on temporal isolation (Bui et al 2011). The idea here is to statically partition the use of shared resources, e.g.…”

Section: Introductionmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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Temporal isolation on multiprocessing architectures

Cited by 49 publications

References 21 publications

A generic and compositional framework for multicore response time analysis

A generic and compositional framework for multicore response time analysis

A Comprehensive Technological Survey on Dependable Self-Managing CPS: The Decade of Researches on Correctness and Dependability

An extensible framework for multicore response time analysis

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