An extensible framework for multicore response time analysis

Abstract

In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize Execution Time, Reliability, Power Consumption and Temperature in Multicores

“…WCET analysis has been applied with success to real-life single-core processors actually used in embedded systems, with branch prediction [19] or with caches and pipelines [20]. These methods have later been adapted to multicores [21]- [23], taking into account the shared resources in the multicore (e.g., the shared memory or the bus).…”

“…(41) and (42) are for the cores; for the bus it suffices to replace F ik by F b ik and to take the value of parameter a corresponding to the bus. Based on these equations, the main objective of ILP is to minimize the total the execution length (the W variable in our ILP formulation), under the constraints specified by Eqs (23) to (42). In Section V-D, we will compare the Pareto fronts computed respectively by our quad-criteria heuristic ERPOT and by an ILP program.…”

Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling

“…Rihani et al [44] in their work build upon the generic framework developed in [3] to compute the impact of interference specifically for synchronous data flow graphs. Davis et al [15] consider the memory demand and processor demand of each task and hence use it to compute the interference caused by the execution of a given task on the system, thus providing a more exact solution than [3]. Kang et al [26] in their work compute the interference that rises from all 4 possible types of communication i.e.…”

Work-in-Progress: Design-Space Exploration of Multi-Core Processors for Safety-Critical Real-Time Systems

“…It can model variable number of cores, with different arbitration policies, as well as multifarious memory models (uncached systems, data and instruction caches, scratchpads, etc., and any combination of them). We refer to [1] and [2] for details on the MRTA framework.…”