FPGA Based True Random Number Generators Using Non-Linear Feedback Ring Oscillators

Tao, Shiquan; Yu, Yang; Dubrova, Elena

doi:10.1109/newcas.2018.8585569

Cited by 13 publications

(9 citation statements)

References 4 publications

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“…NLFIRO TRNG. Non-linear feedback ring oscillators (NLFRO) [16] enhance the design of ring oscillators by incorporating a non-linear feedback function. NLFRO-based TRNGs harvest their high entropy from different sources, namely, noise and variation in delay cells, unpredictable behavior in astable logic elements, and non-linear feedback loops.…”

Section: Digital Noise Sourcesmentioning

confidence: 99%

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On the Effectiveness of True Random Number Generators Implemented on FPGAs

Galli

Galimberti²,

Fornaciari³

et al. 2022

Lecture Notes in Computer Science

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Randomness is at the core of many cryptographic implementations. True random number generators provide unpredictable sequences of numbers by exploiting physical phenomena. This work compares multiple literature proposals of true random number generators targeting FPGAs. The considered TRNGs are obtained as the combinations of three digital noise sources, namely, NLFIRO, PLL-TRNG, and ES-TRNG, and three post-processing techniques, namely, XOR, Von Neumann, and LFSR. The resulting combinations of such components are evaluated in terms of security, throughput, and resource utilization. The experimental results, which were collected on Xilinx Artix-7 FPGAs, highlight the importance of the post-processing stage for security purposes and reveal NLFIRO as the best digital noise source and LFSR as the best post-processing technique, having the highest throughput with excellent security performance without compromising area and power consumption.Keywords: Field programmable gate arrays • True random number generators • Hardware-based security primitives • Side-channel attacks Supported by the EU Horizon 2020 "TEXTAROSSA" project (Grant No. 956831).

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Section: Digital Noise Sourcesmentioning

confidence: 99%

“…We implement the Fibonacci configuration of the NLFRO with nine stages and three NOT gates as inverter chain, which is referred to as NLFIRO [16]. Figure 2 depicts the architecture of the implemented NLFIRO, whose feedback function is shown in Eq.…”

Section: Digital Noise Sourcesmentioning

confidence: 99%

On the Effectiveness of True Random Number Generators Implemented on FPGAs

Galli

Galimberti²,

Fornaciari³

et al. 2022

Lecture Notes in Computer Science

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“…In the implementation of TRNG, feedback architecture is usually applied to improve performance 18–24 . Tehranipoor et al 18 proposed a dynamic voltage feedback tuning circuit in a power supply noise‐based TRNG, to create self‐adjusting operation in the face of voltage fluctuation.…”

Section: Introductionmentioning

confidence: 99%

“…Sala et al 21 designed a feedback strategy to randomly vary the least significant bits that set the duration of the excitation time in ROs, in order to improve the randomness of TRNG. Tao et al 22 presented a nonlinear feedback RO, which was suitable for implementing high entropy, high speed, and attack resistance TRNGs. Cui et al 23 used a multi‐stage feedback RO to enlarge the range of clock jitter and improve the frequency of clock sampling and the randomness of the entropy source.…”

Section: Introductionmentioning

confidence: 99%

“…In the implementation of TRNG, feedback architecture is usually applied to improve performance. [18][19][20][21][22][23][24] Tehranipoor et al 18 proposed a dynamic voltage feedback tuning circuit in a power supply noise-based TRNG, to create selfadjusting operation in the face of voltage fluctuation. Kim et al 19 presented a differential RO cell with feedback resistors to overcome the process variation effects in TRNG.…”

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confidence: 99%

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A true random number generator with high bit rate and low energy efficiency

Cheng

Zhang

Zhu

et al. 2023

Circuit Theory & Apps

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Summary In this paper, a novel feedback architecture of true random number generator based on tetrahedral ring oscillator is proposed. The random raw bits are fed back to produce control voltages, which control the transmission gates in ring oscillators. Since random fluctuations of the control voltages increase the phase jitter of the oscillator, this architecture improves the bit rate and randomness of random sequence. Besides, a post‐processor is designed to enhance the randomness further. The circuit is implemented in TSMC 40‐nm complementary metal oxide semiconductor (CMOS) process, and it takes up an area of 85 × 51 μm. Measurement results show that the random number sequences pass the statistical randomness tests, with a low power consumption of 67 μW, high speed of 45 Mbps, and low energy efficiency of 1.48 pJ/bit.

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