Summary
In this paper, a novel feedback architecture of true random number generator based on tetrahedral ring oscillator is proposed. The random raw bits are fed back to produce control voltages, which control the transmission gates in ring oscillators. Since random fluctuations of the control voltages increase the phase jitter of the oscillator, this architecture improves the bit rate and randomness of random sequence. Besides, a post‐processor is designed to enhance the randomness further. The circuit is implemented in TSMC 40‐nm complementary metal oxide semiconductor (CMOS) process, and it takes up an area of 85 × 51 μm. Measurement results show that the random number sequences pass the statistical randomness tests, with a low power consumption of 67 μW, high speed of 45 Mbps, and low energy efficiency of 1.48 pJ/bit.
SummaryIn this paper, a hybrid architecture of digital pulse width modulator (DPWM) which applies a counter, a phase‐shifted circuit, and a carry chain is proposed. Dual‐edge‐triggered flip‐flops are used in the phase‐shifted circuit to generate signals with 45° phase shift, which not only improves the resolution of the DPWM but also reduces the resource consumption in the carry chain. Furthermore, a hardware compensation method is used to solve the duty cycle increment phenomenon that affects the regulation accuracy of converter. An 11‐bit DPWM with the proposed architecture is implemented and tested by Xilinx Artix‐7 FPGA. The experimental results show a high resolution of 32 ps and a good linearity where R2 is 0.99 and verify the effect of duty cycle compensation.
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