On the Effectiveness of True Random Number Generators Implemented on FPGAs

Galli, Davide; Galimberti, Andrea; Fornaciari, William; Zoni, Davide

doi:10.1007/978-3-031-15074-6_20

Cited by 3 publications

(1 citation statement)

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“…In this paper, DDMTD technology is used to determine the phase difference of the master and slave clocks. After obtaining the phase difference, the Xilinx 7 series FPGA [30,31] is used for functional verification, and the clock PLL of the FPGA is used to shift the synchronized slave clock phase, so as to achieve high-precision synchronization of the sampling clock of the TI-ADC [32,33]. In this paper, the asynchronous router's clock at 250 MHz is used for the sampling clock.…”

Section: The Implementation Of Ddmtd (1) Phase Discrimination Of Mast...mentioning

confidence: 99%

Research on Clock Synchronization of Data Acquisition Based on NoC

Meng,

Xu,

Liao

2024

Applied Sciences

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Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock’s phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps.

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Section: The Implementation Of Ddmtd (1) Phase Discrimination Of Mast...mentioning

confidence: 99%

Research on Clock Synchronization of Data Acquisition Based on NoC

Meng,

Xu,

Liao

2024

Applied Sciences

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FPGA-Based Design and Implementation of a Code-Based Post-quantum KEM

Galimberti

2024

SpringerBriefs in Applied Sciences and Technology

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Post-quantum cryptography aims to design cryptosystems that can be deployed on traditional computers and resist attacks from quantum computers, which are widely expected to break the currently deployed public-key cryptography solutions in the upcoming decades. Providing effective hardware support is crucial to ensuring a wide adoption of post-quantum cryptography solutions, and it is one of the requirements set by the USA’s National Institute of Standards and Technology within its ongoing standardization process. This research delivers a configurable FPGA-based hardware architecture to support BIKE, a post-quantum QC-MDPC code-based key encapsulation mechanism. The proposed architecture is configurable through a set of architectural and code parameters, which make it efficient, providing good performance while using the resources available on FPGAs effectively, flexible, allowing to support different large QC-MDPC codes defined by the designers of the cryptosystem, and scalable, targeting the whole Xilinx Artix-7 FPGA family. Two separate modules target the cryptographic functionality of the client and server nodes of the quantum-resistant key exchange, respectively, and a complexity-based heuristic that leverages the knowledge of the time and space complexity of the configurable hardware components steers the design space exploration to identify their best parameterization. The proposed architecture outperforms the state-of-the-art reference software that exploits the Intel AVX2 extension and runs on a desktop-class CPU by 1.77 and 1.98 times, respectively, for AES-128- and AES-192-equivalent security instances of BIKE, and it provides a speedup of more than six times compared to the fastest reference state-of-the-art hardware architecture, which targets the same FPGA family.

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