Flip chip as an enabler for MEMS packaging

Boustedt, K.; Persson, Katarina; Stranneby, Dag

doi:10.1109/ectc.2002.1008084

Cited by 10 publications

(3 citation statements)

References 16 publications

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“…The packaging of MEMS can not only protect the micro-device from mechanical and environmental damage, but can also solve the problem of the heat dissipation of the chip. Many MEMS packaging techniques have been proposed to package the micro-system, such as the flip chip packaging technique [38,39], multichip component technique [40,41], multichip packaging technique [42,43], wafer level packaging technique [44,45], and three-dimensional (3D) integration packaging technique [46,47].…”

Section: Introductionmentioning

confidence: 99%

A review: wafer bonding of Si-based semiconductors

Chen

2020

J. Phys. D: Appl. Phys.

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Wafer bonding techniques, which are very different from epitaxial growth techniques, can be used not only for the fabrication of micro-electromechanical systems (MEMS), silicon on insulator (SOI), and Si-based device integration, but have recently been applied to the achievement of high-quality homojunctions and heterojunctions in the photoelectric field. That is, carrier transport at the interface of the wafer-bonded junction should be unimpeded and carrier recombination at the bonded interface should be restrained. For Si/Si wafer bonding, although a high bonding strength and a bubble-free bonded interface are needed for the fabrication of the MEMS and SOI, a perfect Si/Si bonded interface which is expected to be bubble-free, oxide-layer-free, and dislocation-free is needed for the achievement of high-performance photoelectric devices, such as Ge/Si single-photon avalanche photodiodes. On the other hand, for Ge/Si heterogeneous hybrid integration (high lattice mismatch), threading dislocations (TDs) in the Ge film can be eliminated by low-temperature heterogeneous wafer bonding, due to the lower diffusion rate of misfit dislocations (MDs) at the Ge/Si bonded interface. This is very different from epitaxial growth, in which high-density TDs form in the integrated Ge layer due to the threading of MDs at high-temperature. In this paper, we review the wafer bonding of Si-based semiconductors based on different bonding methods. The advantages and disadvantages of different bonding methods are pointed out for comparison. We focus on the illustration of the fabrication of Si/Si and Ge/Si wafer pairs with TD-free, bubble-free, and oxide-layer-free bonded interfaces. Finally, the outlook for the development of Si/Si and Ge/Si wafer bonding and devices based on the wafer bonding technique is considered. We trust that this work may provide guidance for the low-temperature heterogeneous hybrid integration of different group materials with ultrahigh lattice mismatch, such as GeSn on Si and III-V materials on Si.

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Section: Introductionmentioning

confidence: 99%

A review: wafer bonding of Si-based semiconductors

Chen

2020

J. Phys. D: Appl. Phys.

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“…Those studies were mainly focused on the solder joint geometry of BGA packages [3][4][5]. The number of solder joints and the solder joint volume are generally much larger than that of the MOEMS devices packaged by flip chip technology [6]. Because of this, small solder joints with less number of I/Os are focused in this study.…”

Section: Introductionmentioning

confidence: 99%

Determination of solder bump stand-off height in a flip-chip sub-mount for Micro-Opto-Electro-Mechanical System (MOEMS) packaging applications

Lee

et al. 2008

2008 58th Electronic Components and Technology Conference

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Solder is a very common and important material for electronic packaging. The major function of the solder is to provide the electrical connection between different electrical components. In SMT assemblies, solder also provides the mechanical support. Self alignment property of solder joints is one of the advantages of using solder as the interconnection materials in SMT process. It can pull the initially misaligned component back to the desired position by surface tension of the solder during the reflow process.

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“…But in order to realize the encapsulation of miniaturization, the encapsulation mode adopts flip-chip method. The flip-chip is more advanced than wire bonding technology, and it has great potential for development [3,4].…”

Section: Introductionmentioning

confidence: 99%

The finite element analysis of solder joints under temperature cycling

Liu

Lou

Fufu

et al. 2014

2014 Joint IEEE International Symposium on the Applications of Ferroelectric, International Workshop on Acoustic Transduction M

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A thermal-mechanical coupled finite element analysis model of solder joints is established, which plays a role in mechanical support and electrical connection in flip chip. Periodic temperature cycle load (-45 ~125 ) applied on the solder joints and it will generate periodic internal stress and strain in the process of the temperature cycling. With repeat using, the solder joints will produce deformation, and then cracks, extension, interlayer delaminating. The failure of the solder joints may cause the failure of the entire switch. This paper aims to simulate the periodic changes in temperature and obtain the reliability and potential failure modes of solder joints under temperature cycling, thus providing theory reference for the design and application of the novel solid MEMS switch.

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Flip chip as an enabler for MEMS packaging

Cited by 10 publications

References 16 publications

A review: wafer bonding of Si-based semiconductors

A review: wafer bonding of Si-based semiconductors

Determination of solder bump stand-off height in a flip-chip sub-mount for Micro-Opto-Electro-Mechanical System (MOEMS) packaging applications

The finite element analysis of solder joints under temperature cycling

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