Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints

Wang, Yinglei; Yu, Wancong; Wu, Shuo; Malysa, Greg; Suh, G. Edward; Kan, Edwin C.

doi:10.1109/sp.2012.12

Cited by 106 publications

(51 citation statements)

References 21 publications

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“…Random number generators can be broadly classi ed into two categories [32,78,145,148]: 1) pseudo-random number generators (PRNGs) [18,98,100,102,133], which deterministically generate numbers starting from a seed value with the goal of approximating a true random sequence, and 2) true random number generators (TRNGs) [6,16,22,23,24,33,36,47,50,55,56,57,65,77,83,96,101,111,116,119,141,143,144,146,149,151,153,155,158], which generate random numbers based on sampling non-deterministic random variables inherent in various physical phenomena (e.g., electrical noise, atmospheric noise, clock jitter, Brownian motion).…”

Section: Introductionmentioning

confidence: 99%

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

Kim

Patel

Hassan

et al. 2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

105

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We propose a new DRAM-based true random number generator (TRNG) that leverages DRAM cells as an entropy source.The key idea is to intentionally violate the DRAM access timing parameters and use the resulting errors as the source of randomness. Our technique speci cally decreases the DRAM row activation latency (timing parameter t RCD ) below manufacturerrecommended speci cations, to induce read errors, or activation failures, that exhibit true random behavior. We then aggregate the resulting data from multiple cells to obtain a TRNG capable of providing a high throughput of random numbers at low latency.To demonstrate that our TRNG design is viable using commodity DRAM chips, we rigorously characterize the behavior of activation failures in 282 state-of-the-art LPDDR4 devices from three major DRAM manufacturers. We verify our observations using four additional DDR3 DRAM devices from the same manufacturers. Our results show that many cells in each device produce random data that remains robust over both time and temperature variation. We use our observations to develop D-RaNGe, a methodology for extracting true random numbers from commodity DRAM devices with high throughput and low latency by deliberately violating the read access timing parameters. We evaluate the quality of our TRNG using the commonly-used NIST statistical test suite for randomness and nd that D-RaNGe: 1) successfully passes each test, and 2) generates true random numbers with over two orders of magnitude higher throughput than the previous highest-throughput DRAM-based TRNG.

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Section: Introductionmentioning

confidence: 99%

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

Kim

Patel

Hassan

et al. 2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

105

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show abstract

“…In addition, the write failure in SRAM cells caused by reduced write duration or scaled V DD has been exploited to create random digital responses [21], [22]. NVM structures, including emerging ones, e.g., FLASH and phase change memory, are used to construct PUF [25], [26]. The resistance variation in metal interconnects on die has been utilized to design PUF due to its low sensitivity to environmental (e.g., voltage) variations.…”

Section: A Related Workmentioning

confidence: 99%

“…Fig. 11 shows the influence of clock delay lines (i.e., 1,9,17,25, and 32) on the percentage of unstable bits at 40°C, 55°C, and 70°C. Signature robustness is generally enhanced with more clock delay lines, since minor common variations on scan path delays can be detected accurately.…”

Section: Robustnessmentioning

confidence: 99%

DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain

Zheng

Zhang

Bhunia

2016

IEEE Trans. VLSI Syst.

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Physical unclonable function (PUF) has emerged as an attractive primitive to address diverse hardware security issues in integrated circuits, such as authentication and cryptographic key generation. Most of the existing PUFs rely on dedicated circuit structure for generating random signatures. It often causes concerns due to extra design efforts and hardware overhead. Moreover, the hardware complexity increases with higher entropy requirement, which may be unacceptable in areaconstrained applications. In this paper, we propose DScanPUF, a novel PUF structure that leverages on the scan chain, a prevalent design-for-test structure in a chip. It is based on a low-overhead delay measurement structure consisting of a phaselocked loop and multiple clock delay lines to measure scan path delays at high resolution. A method is proposed to transform the responses into robust binary signatures. We note that the area of DScanPUF is only 18% of the ring-oscillator (RO) PUF with 1024 ROs. Moreover, it can be easily integrated into a design without any influence on testability. DScanPUF is evaluated with test results from 31 field-programmable gate array chips, which show good randomness, uniqueness and reproducibility under temperature, and supply voltage fluctuations. We also show that the signature is robust under aging effects on scan paths through a simulation at 45-nm CMOS process. Finally, we propose a simple structural modification to further improve the signature robustness.

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“…In [13], a scheme combining garbage collection and per-page scrubbing is proposed for flash memory. In [14], scrubbing is also utilized to implement flash-based physical unclonable functions (PUF). However, due to program disturb effect 1 [15], scrubbing a page may introduce unpredictable errors to the pages within the same block.…”

Section: Related Work On Ssd Secure Deletionmentioning

confidence: 99%

ErasuCrypto: A Light-weight Secure Data Deletion Scheme for Solid State Drives

Liu

Khouzani

Yang

2016

Proceedings on Privacy Enhancing Technologies

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Securely deleting invalid data from secondary storage is critical to protect users' data privacy against unauthorized accesses. However, secure deletion is very costly for solid state drives (SSDs), which unlike hard disks do not support in-place update. When applied to SSDs, both erasure-based and cryptography-based secure deletion methods inevitably incur large amount of valid data migrations and/or block erasures, which not only introduce extra latency and energy consumption, but also harm SSD lifetime. This paper proposes ErasuCrypto, a light-weight secure deletion framework with low block erasure and data migration overhead. ErasuCrypto integrates both erasurebased and encryption-based data deletion methods and flexibly selects the more cost-effective one to securely delete invalid data. We formulate a deletion cost minimization problem and give a greedy heuristic as the starting point. We further show that the problem can be reduced to a maximum-edge biclique finding problem, which can be effectively solved with existing heuristics. Experiments on real-world benchmarks show that ErasuCrypto can reduce the secure deletion cost of erasurebased scheme by 71% and the cost of cryptographybased scheme by 37%, while guaranteeing 100% security by deleting all the invalid data.

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Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints

Cited by 106 publications

References 21 publications

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain

ErasuCrypto: A Light-weight Secure Data Deletion Scheme for Solid State Drives

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