Figure of merit based design strategy for low-power continuous-time ΣΔ modulators

Continuous-Time Sigma-Delta A/D Conversion

“…The definition of a figure of merit is often taken into consideration to be able to compare different modulator implementations with each other. The most commonly used FOM takes the relation of power consumption over modulator resolution and bandwidth [48].…”

“…was presented in [5]. In [38,48], an approach has been presented that determines the powerefficiency of different modulator structures subject to the required converter resolution and signal bandwidth. This method will be illustrated in detail in the following.…”

“…For low-voltage low-power applications single-loop architectures are the preferred structures over cascaded stages, because they do not put stringent requirements on the amplifiers [34,235] and coefficient matching [37,91], they require only a few critical analog components [48,72] and are very robust if the modulator order is N ≤ 2. But however, low-order single-loop modulators demand high oversampling ratios to achieve the desired resolutions, which accordingly leads to a higher power consumption and increases constraints due to clock jitter and excess loop delay [3,153].…”

“…Estimated FOM as a function of the oversampling ratio OSR corresponding to the design example 1 (12-bit, 25 kHz) for different modulator topologies and orders[48]. (a) Ideal SL; (b) scaled SL; (c) SL Bint = 3; (d) 2-1, 2-2 and 2-1-1 obtained with a third-order modulator with an OSR of approximately 40.…”