Optimization of modulator and circuits for low power continuous-time Delta-Sigma ADC

Marker-Villumsen, Niels; Bruun, Erik

doi:10.1109/norchip.2014.7004723

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…For the implementation of the integrators an RC-integrator topology is used and it was designed accordingly to [5]. It consists of fully-differential operational transconductance amplifier (OTA i ), two integrating capacitors (C i ) and several resistors which implement the coefficients defined in Section III (a i , b i , c i and g i ).…”

Section: A Integrators and Coefficientsmentioning

confidence: 99%

System level design of a continuous-time ΔΣ modulator for portable ultrasound scanners

Muntal

Færch²,

Jørgensen

et al. 2015

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &Amp; International Symposium on System-on-Chip (SoC)

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Abstract-In this paper the system level design of a continuous-time ∆Σ modulator for portable ultrasound scanners is presented. The overall required signal-to-noise ratio (SNR) is derived to be 42 dB and the sampling frequency used is 320 MHz for an oversampling ratio of 16. In order to match these requirements, a fourth order, 1-bit modulator with optimal zero placing is used. An analysis shows that the thermal noise from the resistors and operational transconductance amplifier is not a limiting factor due to the low required SNR, leading to an inherently very low-power implementation. Furthermore, based on high-level VerilogA simulations, the performance of the ∆Σ modulator versus various block performance parameters is presented as trade-off curves. Based on these results, the block specifications are derived.

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Section: A Integrators and Coefficientsmentioning

confidence: 99%