Low power continuous-time delta-sigma ADC with current output DAC

Marker-Villumsen, Niels; Jørgensen, Ivan Harald Holger; Bruun, Erik

doi:10.1109/ecctd.2015.7300096

Cited by 4 publications

(1 citation statement)

References 8 publications

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“…The signal transfer function (STF) and the quantisation noise transfer function (NTF) of each modulator depend on the analogue scaling coefficients. These coefficients are selected in order that minimum quantisation noise, superior signal levels in the transition, and physically realisable blocks such as integrators and digital-to-analogue converters (DACs) could be obtained [16,17]. The analogue scaling coefficients of the modulator are listed in Table 1. IET Circuits Devices Syst., 2019, Vol.…”

Section: -1 Mash Delta-sigma Modulatormentioning

confidence: 99%

2‐1 Switched‐current multi‐stage noise‐shaping delta–sigma modulator with a digital noise‐cancellation circuit

Gunnam

Sung

Weng

et al. 2019

IET Circuits, Devices & Systems

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This study focuses on the design of a 2-1 switched-current (SI) multi-stage noise-shaping delta-sigma modulator with a digital noise-cancellation circuit. The noise-cancellation circuit is designed by employing various algorithms for designing the logic circuits and constructing a delay block with an inverter and a transmission gate. It can eliminate the higher-order quantisation noise from the first stage of the modulator completely. In the proposed differential current-mode sample-and-hold circuit, low-input impedance is presented with feedback and width-length adjustment in SI feedback memory cell, a coupled differential replicate with the common-mode feed-forward (CMFF) circuit is used to stabilise the common-mode bias voltage at input terminal, and a differential cross-connected CMFF circuit is utilised to fix the bias voltages. Post-layout simulations reveal that the simulated signal-to-noise-and-distortion ratio (SNDR) was 90.4 dB and the effective number of bit (ENOB) was 14.73 bits. Measurements show that the SNDR was 59.13 dB and the ENOB was 9.53 bits at a sampling rate of 10.24 MHz, an oversampling ratio of 256, and a signal bandwidth of 20 kHz. This design has a power requirement of 12.99 mW from a supply voltage of 1.8 V and occupies a core area of 0.14 mm 2 .

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Section: -1 Mash Delta-sigma Modulatormentioning

confidence: 99%

2‐1 Switched‐current multi‐stage noise‐shaping delta–sigma modulator with a digital noise‐cancellation circuit

Gunnam

Sung

Weng

et al. 2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

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Sigma-delta ADC based adaptive readout ASIC for digital audio sensor

Zou¹,

Rocca²,

Blasi³

et al. 2017

Analog Integr Circ Sig Process

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Digital Noise-Cancellation Circuit Implementation Using Proposed Algorithm and Karnaugh Map in a MASH 2-1 Delta-Sigma Modulator

Xiao

Huang

Sung

et al. 2022

J CIRCUIT SYST COMP

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This paper presents the implementation of two digital noise-cancellation circuits (DNCCs) using a proposed algorithm and a Karnaugh map for a [Formula: see text] multistage noise-shaping (MASH) delta-sigma modulator (DSM). The MASH architecture inherits a superior signal-to-noise-and-distortion ratio (SNDR) with the aid of an efficient noise-cancellation technique either in the analogue or digital domain. The key motivation of this study was to design an area-efficient DNCC. The first approach employed a proposed algorithm (Algorithm-based DNCC) to implement the DNCC and to construct a delay block with an inverter and transmission gate. The second approach involved a Karnaugh map (K-map DNCC) and a delay block with a pair of D flip-flops. A maximum simulated signal-to-noise ratio of 135[Formula: see text]dB was completed with optimal analogue scaling coefficients for the proposed [Formula: see text] MASH DSM with DNCC. The simulated SNDRs of the Algorithm-based DNCC and K-map DNCC were 91.04[Formula: see text]dB and 91.16[Formula: see text]dB, respectively. Measured results show that the SNDR of the Algorithm-based DNCC, the SNDR of the K-map DNCC, power consumption and core area are approximately 58.7[Formula: see text]dB, 62.1[Formula: see text]dB, 0.26[Formula: see text][Formula: see text]W and 2275[Formula: see text][Formula: see text]m2, respectively, for the designed DNCCs with an operating frequency of 10.24[Formula: see text]MHz and supply voltage of 1.8[Formula: see text]V. The transistor counts of the Algorithm-based DNCC are 74 transistors, while they are 106 transistors for the K-map DNCC. The proposed Algorithm-based DNCC saves 32 transistors and approximately reduces its chip area to 69.8% of the K-map DNCC.

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Low power continuous-time delta-sigma ADC with current output DAC

Cited by 4 publications

References 8 publications

2‐1 Switched‐current multi‐stage noise‐shaping delta–sigma modulator with a digital noise‐cancellation circuit

2‐1 Switched‐current multi‐stage noise‐shaping delta–sigma modulator with a digital noise‐cancellation circuit

Sigma-delta ADC based adaptive readout ASIC for digital audio sensor

Digital Noise-Cancellation Circuit Implementation Using Proposed Algorithm and Karnaugh Map in a MASH 2-1 Delta-Sigma Modulator

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