Digital Noise-Cancellation Circuit Implementation Using Proposed Algorithm and Karnaugh Map in a MASH 2-1 Delta-Sigma Modulator

Abstract

This paper presents the implementation of two digital noise-cancellation circuits (DNCCs) using a proposed algorithm and a Karnaugh map for a [Formula: see text] multistage noise-shaping (MASH) delta-sigma modulator (DSM). The MASH architecture inherits a superior signal-to-noise-and-distortion ratio (SNDR) with the aid of an efficient noise-cancellation technique either in the analogue or digital domain. The key motivation of this study was to design an area-efficient DNCC. The first approach employed a proposed algorithm (Algorithm-based DNCC) to implement the DNCC and to construct a delay block with an inverter and transmission gate. The second approach involved a Karnaugh map (K-map DNCC) and a delay block with a pair of D flip-flops. A maximum simulated signal-to-noise ratio of 135[Formula: see text]dB was completed with optimal analogue scaling coefficients for the proposed [Formula: see text] MASH DSM with DNCC. The simulated SNDRs of the Algorithm-based DNCC and K-map DNCC were 91.04[Formula: see text]dB and 91.16[Formula: see text]dB, respectively. Measured results show that the SNDR of the Algorithm-based DNCC, the SNDR of the K-map DNCC, power consumption and core area are approximately 58.7[Formula: see text]dB, 62.1[Formula: see text]dB, 0.26[Formula: see text][Formula: see text]W and 2275[Formula: see text][Formula: see text]m2, respectively, for the designed DNCCs with an operating frequency of 10.24[Formula: see text]MHz and supply voltage of 1.8[Formula: see text]V. The transistor counts of the Algorithm-based DNCC are 74 transistors, while they are 106 transistors for the K-map DNCC. The proposed Algorithm-based DNCC saves 32 transistors and approximately reduces its chip area to 69.8% of the K-map DNCC.