A 1 V, 12-bit wideband continuous-time ΣΔ modulator for UMTS applications

Continuous-Time Sigma-Delta A/D Conversion

“…Concluding, single-loop CT Σ∆ modulators appear quite tolerant against integrator gain variations, and they can be built without severe performance degradation over a wide range [36]. In contrast, cascaded CT Σ∆ modulators cannot be implemented with an acceptable resolution without any countermeasures against the influence of gain errors [20,125].…”

“…-And finally the contributions of the authors themselves in the theoretical modeling, error correction as well as implementation of continuous-time Σ∆ modulators, beyond others [29][30][31][32][33][34][35][36][37][38].…”

“…3.2b) implementation [3,54,112,113,123]. These are particularly advantageous, because their waveforms can be generated by simply switching the feedback current or voltage sources on and off by using the system clock and its edges [36]. On the other hand, from the rectangular feedback realization one major nonideality arises, i.e., the purity of the sampling clock: any timing jitter in the sampling clock modulates directly the ADC decision point as well as the rising and falling edges of the DAC output and thus the quantity of the DAC feedback signals.…”

“…Without loss of generality, the CT scaling coefficients in Fig. 3.6a are moved into the feedback path [34,36], which can be used in order to account for some nonideal behavior, as will be further discussed in Chap. 5.…”

“…As an example, the above estimated loop filter is mapped to a third-order Σ∆ modulator with distributed feedback, as shown in Fig. 3.9 [36]. Doing so, the scaling coefficients k i yield {k 1 , k 2 , k 3 , γ} = {0.51, 0.97, 1.95, 0.04/(k 2 k 3 )}.…”