Fiber-chip edge coupler with large mode size for silicon photonic wire waveguides

Abstract

Fiber-chip edge couplers are extensively used in integrated optics for coupling of light between planar waveguide circuits and optical fibers. In this work, we report on a new fiber-chip edge coupler concept with large mode size for silicon photonic wire waveguides. The coupler allows direct coupling with conventional cleaved optical fibers with large mode size while circumventing the need for lensed fibers. The coupler is designed for 220 nm silicon-on-insulator (SOI) platform. It exhibits an overall coupling efficiency exceeding 90%, as independently confirmed by 3D Finite-Difference Time-Domain (FDTD) and fully vectorial 3D Eigenmode Expansion (EME) calculations. We present two specific coupler designs, namely for a high numerical aperture single mode optical fiber with 6 µm mode field diameter (MFD) and a standard SMF-28 fiber with 10.4 µm MFD. An important advantage of our coupler concept is the ability to expand the mode at the chip edge without leading to high substrate leakage losses through buried oxide (BOX), which in our design is set to 3 µm. This remarkable feature is achieved by implementing in the SiO upper cladding thin high-index SiN layers. The SiN layers increase the effective refractive index of the upper cladding near the facet. The index is controlled along the taper by subwavelength refractive index engineering to facilitate adiabatic mode transformation to the silicon wire waveguide while the Si-wire waveguide is inversely tapered along the coupler. The mode overlap optimization at the chip facet is carried out with a full vectorial mode solver. The mode transformation along the coupler is studied using 3D-FDTD simulations and with fully-vectorial 3D-EME calculations. The couplers are optimized for operating with transverse electric (TE) polarization and the operating wavelength is centered at 1.55 µm.

Edge Couplers in Silicon Photonic Integrated Circuits: A Review

“…Grating couplers have some major advantages including compact size, wafer-level testing capability, and flexible coupling position, while there are also some drawbacks such as a relatively low coupling efficiency typically below 3 dB, narrow bandwidth, and high wavelength sensitivity. As for the butt coupling regime, under which the fiber is typically placed at the wafer facet and aligned with the Si waveguides horizontally, edge couplers are commonly applied [24][25][26][27][28][29][30][31][32]. Edge couplers can achieve rather high coupling efficiency, broad bandwidth, and polarization independence, but they also have some limitations including relatively a larger footprint than grating couplers, fixed coupling position, and more strict requirements of the coupling facet.…”

High-efficiency grating-couplers: demonstration of a new design strategy

“…Among the various proposed solutions, two different approaches have attracted most attention: edge-coupling and grating-coupling. By exploiting edge-coupling, insertion losses lower than 0.5 dB can be achieved over a broad bandwidth (>100 nm) 10 . Nevertheless, this technique requires complicated post-fabrication processes, such as high quality facet polishing, and high-resolution optical alignment, making it not suitable for wafer-level testing and high-volume manufacturing.…”

Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices

“…A number of research groups and companies are working to develop schemes that reduce the alignment tolerance of edge-coupling [21,22]. The aim is to relax the alignment tolerance (or strengthen the fabrication tolerance [23]) to a level that supports multi-channel edge-coupling for telecom and datacom applications.…”

“…High-speed SMA (18)(19)(20)(21)(22)(23)(24)(25) and SMK (46 GHz) connectors have a ≈1 cm 2 footprint on the PCB, while the pitch of the electrical bond-pads on a PIC is typically 100 μm. Therefore, the pitch of the high-speed 50 Ω transmission lines must be reduced by two orders-of-magnitude between the connector and the PIC, while maintaining the path-length of different electrical-channels to preserve signal timings.…”