FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs

Bombieri, Nicola; Fummi,; Guarnieri,

doi:10.1109/date.2012.6176532

Cited by 10 publications

(10 citation statements)

References 13 publications

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“…The framework fully exploits the intrinsic parallelism of RTL SystemC descriptions, by limiting synchronization events with ad-hoc static scheduling and separate independent dataflows. Finally, SystemC simulation on CUDA has been proposed in [4], where the authors propose a framework for functional verification of RTL designs. The framework translates the RTL code into C code targeting NVIDIA GPUs, thus allowing fast parallel automatic test pattern generation and fault simulation.…”

Section: Related Workmentioning

confidence: 99%

SystemC simulation on GP-GPUs

Bombieri

Vinco

Bertacco

et al. 2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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SystemC is a widespread language for developing SoC designs. Unfortunately, most SystemC simulators are based on a strictly sequential scheduler that heavily limits their performance, impacting verification schedules and time-to-market of new designs. Parallelizing SystemC simulation entails a complete re-design of the simulator kernel for the specific target parallel architectures. This paper proposes an automatic methodology to generate a parallel SystemC simulator kernel, exploiting the massive parallelism of GP-GPU architectures. Our solution leverages static scheduling to reduce synchronization overheads. The generated simulator code targets both CUDA and OpenCL libraries, to boost scalability and provide support for multiple GP-GPU architectures. Finally, the paper compares the performance of our solution on CUDA vs. OpenCL platforms, with the goal of investigating advantages and drawbacks that the two thread management libraries offer to concurrent SystemC simulation.

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Section: Related Workmentioning

confidence: 99%

SystemC simulation on GP-GPUs

Bombieri

Vinco

Bertacco

et al. 2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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“…To achieve this, several approaches have been recently investigated, such as mutation schema [21], model abstraction [28], hardware acceleration [29], software emulation [30], and directed test generation [20,22].…”

Section: Testbench Qualificationmentioning

confidence: 99%

Safety Evaluation of Automotive Electronics Using Virtual Prototypes

Oetjens

Bannow

Becker

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.

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“…RTL-to-SystemC/C/C++ translation has been proposed in different works [23,24] and tools [9,25,26] targeting simulation in conventional CPU architectures. The translation from RTL to C for GP-GPUs (i.e., NVIDIA CUDA) has been investigated only in most recent works [10][11][12]. All these works focus on improving simulation performance by parallelizing the SystemC kernel activity ( [10,11]) or by parallelizing instances of the design under verification [12].…”

Section: Related Workmentioning

confidence: 99%

“…Finally, portability on many-core architectures is another major limitation of the data type standard library proposed by ASI. Recently, several research groups are investigating new solutions to reduce the simulation time of complex embedded systems by exploiting the high degree of parallelism afforded by today's general purpose graphics processing units (GP-GPUs) [10][11][12]. All these works present promising techniques that sensibly reduce the simulation time of SystemC models described at any level of abstraction and run on NVIDIA CUDA platforms [13].…”

Section: Introductionmentioning

confidence: 99%

HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels

Bombieri

Fummi

Guarnieri

et al. 2012

Des Autom Embed Syst

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SystemC is the de-facto standard language for system-level modeling, architectural exploration, performance analysis, software development, and functional verification of embedded systems. Nevertheless, it has been proved that the performance of the SystemC implementation is typically less optimal than commercial VHDL/Verilog simulators when used for register transfer level (RTL) simulation. This is mainly due to the "slow" implementation of bit-accurate data types provided by the standard library. Such a problem limits the simulation performance even when SystemC designs are implemented at higher levels of abstraction (i.e., transaction-level modeling-TLM) and still make use of bit-accurate data types (e.g., for a more accurate verification, or in TLM descriptions automatically generated from RTL). This article presents HDTLib, a new bit-accurate data type library that increases the simulation speed up to 3.45× at RTL and up to 10× at TLM. In addition, when the level of abstraction rises from RTL and better simulation performance is required, accuracy of HW-dependent behaviors is no longer necessary. Thus, the article presents a type abstraction methodology to get rid of low level behaviors and how such a methodology can be combined with HDTLib for guaranteeing a sound tradeoff between accuracy and simulation speed. Finally, more recent works have proposed efficient and promising techniques to boost SystemC simulation through general purpose graphics processing unit (GP-GPU) architectures. In such parallel frameworks, the standard SystemC library for bit-accurate data types

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FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs

Cited by 10 publications

References 13 publications

SystemC simulation on GP-GPUs

SystemC simulation on GP-GPUs

Safety Evaluation of Automotive Electronics Using Virtual Prototypes

HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels

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