Safety Evaluation of Automotive Electronics Using Virtual Prototypes

Oetjens, Jan-Hendrik; Bannow, Nico; Becker, Markus; Bringmann, Oliver; Burger, Andreas; Chaari, Moomen; Chakraborty, Samarjit; Drechsler, Rolf; Ecker, Wolfgang; Grüttner, Kim; Kruse, Thomas; Kuznik, Christoph; Le, Hoang M.; Mauderer, Andreas; Müller, Wolfgang; Muller-Gritschneder, Daniel; Poppen, Frank; Post, Hendrik; Reiter, Sebastian; Rosenstiel, Wolfgang; Roth, Sébastien; Schlichtmann, Ulf; Schwerin, A. v.; Tabacaru, Bogdan-Andrei; Viehl, Alexander

doi:10.1145/2593069.2602976

Cited by 44 publications

(18 citation statements)

References 36 publications

(31 reference statements)

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“…Several recent works [7], [22] have been carried out showing the potential and limitations of TSIM-based fault injection. In this paper, we tackle the problem of increasing the confidence on TSIM-based fault injections from a different angle.…”

Section: Introductionmentioning

confidence: 99%

Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection

Espinosa

Hernández

Abella

2016

2016 IEEE 22nd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Abstract-Future high-performance safety-relevant applications require microcontrollers delivering higher performance than the existing certified ones. However, means for assessing their dependability are needed so that they can be certified against safety critical certification standars (e.g ISO26262). Dependability assessment analyses performed at high level of abstraction inject single faults to investigate the effects these have in the system. In this work we show that single faults do not comprise the whole picture, due to fault multiplicities and reactivations. Later we prove that, by injecting complex fault models that consider multiplicities and reactivations in higher levels of abstraction, results are substantially different, thus indicating that a change in the methodology is needed. I. INTRODUCTIONTechnology scaling has allowed processor's semiconductors industry achieving performance numbers beyond Gigaflops with reduced power budget by including a vast number of computational nodes in the same chip [1]. In the safety critical domain the huge amount of available processing power is expected to fullfil the high demands for performance guarantees of new applications like autonomous driving systems [10]. However, hardware systems targeting safety critical applications need to go through a certification process step validating its compliance with the standards [9] [5].The need for a thorough verification and test process that certification standards poses to hardware systems may preclude the use of complex hardware platforms in the context of critical applications. Currently, the verification and test process takes between 50% and 70% of the design effort for a simple microcontroller [8]. Therefore, if high-complexity processors are to be considered for highly critical applications, like ASIL-D in the automotive domain, new methodologies and tools for the robustness verification step have to be devised [2].Safety-critical systems industry uses simulation-based verification as a way to reduce the costs associated with the verification and validation of complex designs. Simulation-based verification allows reducing verification and validation costs as design threats and certification mismatches can be detected before manufacturing. Simulation-based robustness verification is typically carried out at RTL and gate-levels by performing extensive fault-injection campaigns that require huge computation effort to achieve meaningful results. Further increasing the level of abstraction of simulation-based fault injection will allow reducing verification costs of current designs and affording the simulation effort of high-complexity processor designs. In the case of microcontrollers, the instruction set simulator (a.k.a. TSIM) has been regarded as a potential candidate to carry out the robustness verification at a high level of abstraction. However, for TSIM's to be used in the robustness verification process it must be proven that by leveraging them accurate results can be achieved.

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Section: Introductionmentioning

confidence: 99%

Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection

Espinosa

Hernández

Abella

2016

2016 IEEE 22nd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…Fault injection using simulation can be performed using different levels of abstraction like functional, RTL, or gate-level. The current state of practice uses RTL and gate-level experiments to test hardware robustness as these methodologies have been shown to provide good accuracy [123]. A commonality of every simulation methodology is that it has to be related with the techniques used at silicon level for validation.…”

Section: G2 Towards Simulation-based Robustness Verificationmentioning

confidence: 99%

“…Fault injection methodologies are widely employed for the microcontrollers robustness verification in the automotive domain [123]. Fault injection experiments can be performed at several abstraction levels to exploit the existing accuracy cost trade-off [175].…”

Section: G5 Related Workmentioning

confidence: 99%

“…Fault injection through simulation can be performed using different levels of abstraction like functional, RTL, or gate-level. The current state of practice uses RTL and gate-level experiments to test hardware robustness as these methodologies have been shown to provide enough accuracy when related to the silicon level [123]. In the same way, if microarchitectural simulators are to be considered for the robustness verification process, results obtained at this level must be correlated with the ones obtained at lower levels of abstraction like the RTL or gate-level.…”

Section: H2 Background On Simulation-based Robustness Verificationmentioning

confidence: 99%

“…Software-based fault injection techniques and in particular fault-injection experiments using virtual prototypes (or microarchitectural simulators) are a potential candidate to reduce the costs associated with the robustness verification process [123] [175]. The main benefits of these approaches with respect to RTL-based fault injections are the simulation speed and the possibility to anticipate deviations w.r.t.…”

Section: F1 Introductionmentioning

confidence: 99%

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New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs

García¹

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"The problem with the world is that the intelligent people are full of doubts, while the stupid ones are full of confidence." Charles Bukowski AgraïmentsVolguera començar agraïnt totes aquelles persones que han fet possible que esta tesi esdevinguera realitat. A totes aquelles persones i que m'han acompanyat durant tot este temps, amb el seu suport tècnic, lingüístic, físic, econòmic o psicològic. Primerament, agrair els meus directors els doctors David de Andrés i Juan CarlosRuiz per la seua dedicació, suport i ànim durant estos anys. Heu sigut de gran ajuda. També al professor Pedro Gil per confiar en mi i donar-me el recolzament econòmic i científic per portar a terme el projecte.Així mateix, també volguera tenir unes paraules per als meus companys del grup de Sistemes Tolerants a Fallades (STF) i en especial als del laboratori: el ja doctor Jesus Friginal, Miquel Martinez, Héctor Marco, Javier Cancio i Antonio Bustos. Haveu sigut els millors, i junts hem passat molt bons moments. També agrair els companys de l'estada a Edinburgh Félix Casado i Ali Ebrahim, i molt especialment als del Barcelona Supercomputing Center Carles, Jaume, Mikel, Javi, Maria, David, Roberto, Milos, Mladen, Suzanna, Quixiao, Leonidas i la resta del grup CAOS per fer-me sentir com a casa.Per descomptat que no només he rebut suport dels companys de recerca. Per això he d'esmentar la meua estimada Sara, per donar-me tot el suport i l'estima possibles i impossibles, i els meus pares i germans, perquè sempre han estat fentme costat i m'han animat a seguir estudiant per comprendre millor el món que ens envolta.Finalment a les persones de la Universitat en general, i del món científic en particular, a la vocació dels quals devem que el sistema continue funcionant.Jaume.v SumariLa rellevància que l'electrònica adquireix en la seguretat dels productes ha crescut inexorablement, puix cada volta més aquesta abasta una major influència en la funcionalitat dels mateixos. Però, per descomptat, aquest fet ve acompanyat d'un constant necessitat de majors prestacions per acomplir els requeriments funcionals, mentre es mantenen els costos i consums en uns nivells reduïts. Donat aquest escenari, la indústria està fent esforços per proveir una tecnologia que complisca amb totes les especificacions de potència, consum i preu, tot a costa d'un increment en la vulnerabilitat a diversos tipus de fallades conegudes, i a la introducció de nous tipus.Per oferir una solució a les noves i creixents fallades als sistemes, els dissenyadors han recorregut a tècniques tradicionalment associades a sistemes crítics per a la seguretat, que en general oferixen resultats sub-òptims. De fet, les arquitectures empotrades modernes oferixen la possibilitat d'optimitzar les propietats de confiabilitat en habilitar la interacció dels nivells de hardware, firmware i software en el procés. Tot i això eixe punt no està resolt encara. Es necessiten avanços a tots els nivells en l'esmentada direcció per poder assolir els objectius d'una tolerància a fallades flexible, robusta, resili...

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Cross-Layer Resilience Against Soft Errors: Key Insights

Mueller-Gritschneder

Cheng

Sharif

et al. 2020

Dependable Embedded Systems

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Driven by technology scaling, integrated systems become more susceptible to various causes of random hardware faults such as radiation-induced soft errors. Such soft errors may cause malfunction of the system due to corruption of data or control flow, which may lead to unacceptable risks for life or property in safety-critical applications. Hence, safety-critical systems deploy protection techniques such as hardening and redundancy at different layers of the system stack (circuit, logic, architecture, OS/schedule, compiler, software, algorithm) to improve resiliency against soft errors. Here, cross-layer resilience techniques aim at finding lower cost solutions by providing accurate estimation of soft error resilience combined with a systematic exploration of protection techniques that work collaboratively across the system stack. This chapter demonstrates how to apply the cross-layer resilience principle on custom processors, fixed-hardware processors, accelerators, and SRAM memories (with a focus on soft errors) and presents key insights obtained.

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Safety Evaluation of Automotive Electronics Using Virtual Prototypes

Cited by 44 publications

References 36 publications

Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection

Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection

New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs

Cross-Layer Resilience Against Soft Errors: Key Insights

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