Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.
Functional verification is a major part of today's system design task. Several approaches are available for verification on a high abstraction level, where designs are often modeled using MATLAB/Simulink, as well as for RTlevel verification. Different approaches are a barrier to a unified verification flow. For simulation based RT-level verification, an extended test bench concept has been developed at Robert Bosch GmbH. This paper describes how this SystemC-based concept can be applied to Simulink models.
In this paper, we present a flow for integrating hardware descriptions into Simulink simulations. It enables the automatic generation of a Simulink component out of a hardware component model given as RT level VHDL. The approach is based on two steps. The first step transforms the VHDL model to SystemC. In contrast to existing VHDL-to-SystemC transformation tools, the readability and configurability of the input model is preserved. In addition, our approach yields a more exact model, as a custom designed VHDL-like data-type system is employed. The second step generates a specific wrapper to allow the use of the component in a Simulink simulation. This transformation strategy will be evaluated with two industrial automotive electronics hardware designs.
Abstract. Evaluation and refinement of system models often require modifications in the model that follow concrete rules. In this work, a method for a flexible automation of such transformation steps will be presented. It allows savings in development time and reduces the error proneness. Therefore, a tool for rule based manipulation of VHDL design descriptions has been extended to enable its use with system models in C++ and SystemC. An automotive electronics application, the integration of SystemC modules into a MATLAB/Simulink simulation by automatic wrapper generation, will show its use in the design process.
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