Automatic integration of hardware descriptions into system-level models

Görgen, Ralph; Oetjens, Jan-Hendrik; Nebel, Wolfgang

doi:10.1109/ddecs.2012.6219034

Cited by 5 publications

(2 citation statements)

References 4 publications

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“…There are known approaches for creating SystemC models from Verilog (e.g. [3] and [4]) and tools targeting creation of other C++ subsets. [5] discusses a methodology for abstracting RTL descriptions to different TLM levels.…”

Section: Related Workmentioning

confidence: 99%

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores

Abrar

Jenihhin

Raik

2015

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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The rapid increase of embedded systems design complexity has resulted in emergence of design methodologies at higher levels of abstraction such as Electronic System Level (ESL) and Transaction Level Modeling (TLM) with SystemC language as the main instrument. In practice, system architects and system integrators often have access to a library of legacy Register Transfer Level (RTL) IP (Intellectual Property) cores or obtain new ones from IP design houses. To address architectural exploration, early prototyping and simulation performance, such RTL IP cores are manually recreated at more abstract levels, which implies significant and error-prone effort. The current paper proposes an approach for automated abstraction of the computational part of cycle-accurate RTL IP cores to untimed TLM using a novel concept of SystemC-based Loose Models (SCLM). SCLMs provide for an instrument to neglect design model parts irrelevant for particular manipulation step of the abstraction process, thus simplifying the abstraction flow. As a result, the computational complexity of the abstraction process is reduced, thus increasing the overall scalability. The proposed abstraction flow is demonstrated on a set of benchmark designs and the first experimental results prove feasibility of the proposed approach and also show considerable simulation speed-up.

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Section: Related Workmentioning

confidence: 99%

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores

Abrar

Jenihhin

Raik

2015

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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“…It is targeted mainly [7]. It assumes creation of readable SystemC representations from VHDL that are targeted to be wrapped and simulated in the Simulink environment.…”

Section: Related Workmentioning

confidence: 99%

Performance analysis of cosimulating processor core in VHDL and SystemC

Abrar

Kiran

Jenihhin

et al. 2013

2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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Advances in SoC design complexities require newer methodologies and tools. Traditional RTL-level approach has become a bottleneck, resulting in emergence and standardization of SystemC as a design-language. IP design-houses are interested in providing SystemC models of their portfolio IPs, despite already existing VHDL views. This paper describes a methodology to translate existing VHDL IPs to SystemC, ensuring correctness, quality as well as maintainability of the translated code. The standard practice is to translate a subset of IPs at a time and cosimulate with the rest of the system to validate the translated IPs. Hence, this paper explores scenarios that affect the cosimulation performance. Varying cosimulation scenarios affect the performance upto 30%. Both the contributions of this paper, translation methodology and the cosimulation performance-analysis are relevant to a wider SystemC community, including designers and architects. Furthermore, the results can be used for optimizing cosimulation tools as well system-level-models.

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