Experimental investigation of the minimum signal for reliable operation of DRAM sense amplifiers

Geib, H.; Weber, W.; Wohlrab, E.; Risch, L.

doi:10.1109/4.142598

Cited by 21 publications

(5 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The bit line signal sufficient for reliable differential sensing, V sense is much less than that in the case of single-ended sensing. There are three components to the V sense : offset voltage due to transistor parameter mismatches, capacitive asymmetry and the coupling noise [40]. To be specific, we assume that the cross-coupled latchtype sense amplifier is used, because it is both energy efficient and fast [95].…”

Section: Differential Sensing Schemementioning

confidence: 99%

“…Given the large number of the sense amplifiers, at least 5σ margin is necessary, resulting in the 50mV value, which is again not likely to scale down with the feature size. Bit line capacitive asymmetry does not affect the offset voltage as significantly as in [40], because we assume that the sense amplifier in a register file is not directly connected to bit lines. We also add to V sense 10mV for the differential component of the coupling noise [40] (assume that this component scales down with V dd ), and 40mV to make up for the bit line precharge error (bit line signal remained on bit lines from the previous accesses) and the difference in the signal on bit lines and the one on sensing nodes of the sense amplifier.…”

Section: Differential Sensing Schemementioning

confidence: 99%

“…Bit line capacitive asymmetry does not affect the offset voltage as significantly as in [40], because we assume that the sense amplifier in a register file is not directly connected to bit lines. We also add to V sense 10mV for the differential component of the coupling noise [40] (assume that this component scales down with V dd ), and 40mV to make up for the bit line precharge error (bit line signal remained on bit lines from the previous accesses) and the difference in the signal on bit lines and the one on sensing nodes of the sense amplifier. This difference occurs because as the bit line differential signal grows, the signal at the sense amplifier sensing nodes lags in time by τ = (r SAinput + r bitline )C SA (assume that this component does not scale down with V dd ).…”

Section: Differential Sensing Schemementioning

confidence: 99%

See 2 more Smart Citations

Inherently lower-power high-performance superscalar architectures

Zyuban

Kogge

2001

IEEE Trans. Comput.

113

121

View full text Add to dashboard Cite

Victor V. Zyuban When it comes to performance, modern computer design has become a well structured art which starts with instruction sets that maximize opportunities for concurrency, follows through with fast organizational techniques such as pipelining and super scalar execution, and ends with clever macro and circuit designs that are based on inherently fast CMOS fabrication technologies. When it comes to low power, however, exactly the opposite is true. Current techniques start with lowering supply voltages and making process changes to minimize capacitance, followed by some relatively simple techniques for minimizing power for particular logic macros, and then utilizing relatively ad hoc techniques, such as 'sleep modes', at higher levels. This work attempts to reverse this by bringing the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization of high-performance microprocessors at the microarchitecture level. In particular, our work explores solutions to the problem that do not compromise performance. First, major targets for power reduction are identified within microarchitecture, where power is heavily consumed, or will be heavily consumed in next-generation processors. This involves developing energy models for structures where power grows with increasing issue width, such as Register File, Issue Window, Memory Disambiguation Unit, etc. Then, a multicluster microar-CHAPTER 6: IMPLEMENTATION OF THE ENERGY-EFFICIENT MULTI-CLUSTER ARCHITECTURE .

show abstract

Section: Differential Sensing Schemementioning

confidence: 99%

Section: Differential Sensing Schemementioning

confidence: 99%

Section: Differential Sensing Schemementioning

confidence: 99%

See 1 more Smart Citation

Inherently lower-power high-performance superscalar architectures

Zyuban

Kogge

2001

IEEE Trans. Comput.

113

121

View full text Add to dashboard Cite

show abstract

“…The sensing ability of a sense amplifier can be significantly affected by the mismatch of device's V th [25], [26], especially when the local process variation has continually increased in advanced process technologies [5], [6]. V th mismatch may result in a larger input offset voltage for a differential sense amplifier.…”

Section: Th Mismatchmentioning

confidence: 99%

Fault models and test methods for subthreshold SRAMs

Lin

Chen

Yang

et al. 2010

2010 IEEE International Test Conference

View full text Add to dashboard Cite

Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold SRAM design. However, the test methods regarding those newly developed subthreshold SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold SRAM designs into three types, study the faulty behavior of open defects and address decoders faults on each type of designs, and then identify the faults which may not be covered by a traditional SRAM test method. We will also discuss the impact of open defects and threshold-voltage mismatch on sense amplifiers under subthreshold operations. A discussion about the temperature at test is also provided.

show abstract

“…Several analyses have been done on the offset of the cross-coupled pair being used as a sense amplifier [1], [2], [3]. The approach taken in [1], [2] is based on an empirical analysis while [3] presents an analysis of the system which results in series of involved analytical formulas for the mismatch. While cross-coupled pairs have been studied extensively, the additional devices used in practice can alter the basic analysis significantly.…”

Section: Introductionmentioning

confidence: 99%

Design issues in cross-coupled inverter sense amplifier

Hajimiri

Heald

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

View full text Add to dashboard Cite

This paper presents an analytical approach to the design of CMOS cross-coupled inverter sense amplifiers. The effects of the equilibrating transistors and the tail current source on the speed of the sense amplifier are analyzed. An analysis of the offset due to mismatch in various parameters is performed, showing that a complete offset analysis has to account for the cell and bitline structure. A new figure of merit for the offset in the sense amplifier and several new design insights are introduced.

show abstract

Experimental investigation of the minimum signal for reliable operation of DRAM sense amplifiers

Cited by 21 publications

References 10 publications

Inherently lower-power high-performance superscalar architectures

Inherently lower-power high-performance superscalar architectures

Fault models and test methods for subthreshold SRAMs

Design issues in cross-coupled inverter sense amplifier

Contact Info

Product

Resources

About