Design issues in cross-coupled inverter sense amplifier

Abstract

This paper presents an analytical approach to the design of CMOS cross-coupled inverter sense amplifiers. The effects of the equilibrating transistors and the tail current source on the speed of the sense amplifier are analyzed. An analysis of the offset due to mismatch in various parameters is performed, showing that a complete offset analysis has to account for the cell and bitline structure. A new figure of merit for the offset in the sense amplifier and several new design insights are introduced.

Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing

“…P4 and P5 act as a switch to connect the BLs to the DLs. The other 10 transistors (P6 -P10 and N1-N5) form a cross-coupled inverter which amplifies the small voltage difference on the DLs to the full CMOS logic levels [8], [9], [11], [13] and [14]. The new SA is unique in a way that it eliminated the current conveyor and transformed the normally-large BL loads (P0, P1 in Fig.…”

“…As a result, a small-sized transistor P10 can be used, thus significantly reducing the switching time of the cross-couple inverter [14]. At 0.55-V supply voltage, its sensing delay is 4.53 ns and consumes 6.72 W. For the purpose of this paper, we only optimize the SA for it to work at a very low voltage, rather than over a wide range (from 1.8 to 0.55 V), since large transistors will consume a huge amount of power if it operates at 1.8 V. However, it is enough to prove the superiority of the proposed design over its state-of-the-art counterparts.…”

“…The current-mode sense amplifier (SA) has the ability to quickly amplify a small differential signal from the bit-lines (BLs) and data-lines (DLs) to full CMOS logic-level outputs without requiring large voltage swings of these capacitive lines (whose parasitic capacitances are normally referred to as and , respectively). It is widely used as one of the most effective ways to reduce both sensing delay and power consumption of the SRAM [5]- [14]. In this work, we extensively studied the operation of existing SAs, analyzed their weaknesses and proposed a new sensing scheme that has a much higher driving force, hence providing faster sensing delay, lower power consumption, and greater reliability.…”

Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier

“…Therefore, predicting an accurate offset value is essential not only to improve sensing speed and power consumption, but also to increase the yield of the memory [9], [10]. Several works in the literature have been dedicated to investigating the offset behavior of the cross-coupled inverters (henceforth, the two terms cross-coupled and latch-type will be used interchangeably) [1], [2], [7], [11]- [18]. Most of them only dealt with the threshold voltage mismatch, which is claimed as the most influential factor of the input-offset [13], [17].…”

“…Another method to evaluate the offset of the sense amplifier is by applying lump-sum voltage noise sources to the internal nodes of the cross-coupled structure [11]. However, it provides no insight into the causes of the input-offset voltage, hence giving no suggestion on how to reduce the offset.…”