Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Due to parameter fluctuations in scaled technologies, stable operation is critical to obtain high yield low-voltage, low-power SRAM. Recent published works in literature have shown that the conventional 6T SRAM suffers a severe stability degradation due to access disturbances at low-power mode. Thus, several 8T and 10T cell designs have been reported, improving the cell stability. However, they either employ single-ended read port or require too large area. In this paper, we use a fully differential 8T SRAM that allows efficient bit-interleaving to achieve soft-error tolerance with conventional Error Correcting Code (ECC). It also consumes less power when compared to the conventional 6T design. A column-based dynamic supply voltage scheme is utilized to improve both the read noise margin and the write-ability. To verify the technique, a 128 64-bit of the proposed SRAM has been implemented in a standard 65 nm/1 V CMOS process. Simulation results reaffirmed that the proposed design has 2 higher noise margin and consumes 54% less power when compared to the conventional 6T design.Index Terms-Low power SRAM, low voltage SRAM, multiple port SRAM, static-noise-margin-free.
A subthreshold low-noise amplifier optimized for ultra-low-power applications in the ISM band. IEEE Transactions on Microwave Theory and Techniques, 56(2), 286-292.
Content addressable memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line comparison, CAM is power-hungry. Thus, robust, high-speed and low-power sense amplifiers are highly sought-after in CAM designs. In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. Furthermore, we propose an effective gated-power technique to reduce the peak and average power consumption and enhance the robustness of the design against process variations. A feedback loop is employed to auto-turn off the power supply to the comparison elements and hence reduce the average power consumption by 64%. The proposed design can work at a supply voltage down to 0.5 V.Index Terms-CMOS, content addressable memory (CAM), match-line.
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