2005
DOI: 10.1109/ted.2004.842714
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Experimental Behavior of Single-Chip IGBT and COOLMOS Devices Under Repetitive Short-Circuit Conditions

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Cited by 75 publications
(32 citation statements)
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“…From these results and under these test conditions, we may observe that for these tested devices, the ultimate device failure occurred always after about 1.5 ms whatever the short circuit duration when dissipated energy equals or exceeds critical one. These results obtained for a dissipated energy lightly higher than the critical value are completely different compared to those obtained for silicon devices [7,8] where the failure occurs after the turn-off process with a delay time depending on the short circuit duration.…”
Section: Robustness Testscontrasting
confidence: 80%
See 1 more Smart Citation
“…From these results and under these test conditions, we may observe that for these tested devices, the ultimate device failure occurred always after about 1.5 ms whatever the short circuit duration when dissipated energy equals or exceeds critical one. These results obtained for a dissipated energy lightly higher than the critical value are completely different compared to those obtained for silicon devices [7,8] where the failure occurs after the turn-off process with a delay time depending on the short circuit duration.…”
Section: Robustness Testscontrasting
confidence: 80%
“…We have performed robustness tests in order to evaluate the critical energy which represents the limit of dissipated energy during short circuit phase for which failure occurs after only one short circuit [7].…”
Section: Robustness Testsmentioning
confidence: 99%
“…It has been reported that repetitive failures have two different sources: an external one which can be, for example, linked to faulty control signal [22] and an internal one, linked to physical degradation of the power semiconductor. Examples of these internal failures are: bond wire lift off, gate leakage failure and damages on semiconductors chip and solder [18], SiAl contact ageing [21], electro-migration effect [20], latch-up [23]. These internal failures can modify the operating state of the semiconductor and induce abnormal behavior like OC or SC states.…”
Section: Iipower Electronic Architecture Tolerant To Semiconductor Fmentioning
confidence: 99%
“…It has been demonstrated that their limits in operation are mainly thermal [1,2], as their manufacturing trends target at thinner dies and smaller cell pitch [3]. This increases the power density generated within them under operating conditions.…”
Section: Introductionmentioning
confidence: 99%