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International audienceThis paper presents experimental robustness tests made on Silicon Carbide (SiC) MOSFETs and SiC Bipolar Junction Transistors (BJTs) submitted to short-circuit operations (SC) or current limitation modes. For SiC MOSFETs, a gate leakage current is detected before failure without being responsible for the immediate failure. Nevertheless this gate leakage current is not without effect on the integrity of the SiC MOSFETs. Based on several robustness tests performed on SiC MOSFETs and on the comparison with experimental results obtained with SiC BJTs, the paper points out two main failure modes for SiC MOSFETs. The first one results in a simultaneously short circuit between drain and gate and drain and source and the second one in a degradation of the insulation between gate and source leading to a short circuit between gate and source. For some tested devices, the failure appears in a very interesting open state mode between drain and source after physical short-circuit between gate and source with a mode of failure very similar to those observed for SiC BJT

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Electronic power devices used for transportation applications (automotive and avionics) experience severe temperature variations, which promote their thermal fatigue and failure.For example, for power modules mounted on the engine of an aircraft, temperature variations range from -55°C (in the worst case of storage before takeoff) to +200°C (flight). Direct bonded copper (DBC) substrates are used to isolate chips (silicon dies) from their base plates. For large thermal amplitudes, the failure occurs in DBC substrates, which are copper/ceramic/copper sandwiches.The Weibull approach was used to model the brittle fracture of the ceramic layer from a natural defect. Furthermore, geometric singularities in the upper ceramic/copper interface are at the origin of cracks that grow by fatigue along the interface and finally bifurcate and break the ceramic layer.It is discussed how the framework of linear elastic fracture mechanics (LEFM) can be used to characterize the stress field around singularities and the associated risk of failure. These two criteria and the finite element method, allow analysing how a thermal loading history may modify the risk of failure of DBC substrates. It was shown, in particular, that three overcooling cycles should produce an "overload retardation effect". Experimentally, applying 3 "overload cycles" (-70°C,+180°C), prior to thermal fatigue cycles (-30°C, +180°C), increased very significantly the fatigue life of DBC substrates. This result shows that the fatigue life and the reliability of power electronic devices could be optimized using a thermo-mechanical approach of the problem and suitable failure criteria.

The purpose of this paper is to present a complete experimentation of the two failure modes in competition that can appear during short-circuit (SC) fault operation of single-chip 1,2kV SiC MOSFETs from different manufacturers including planar and trench-gate structures, well-known or recent devices. Ruggedness and selective failure modes are identified in relation with the power density dissipated by the chip and the simulated 1D-thermal junction. Finally, the chips of the devices which failed in a "fail-to-open" mode have been studied in order to find the physical reasons of this original and unusual fail-safe mode.