Ensure an original and safe “fail-to-open” mode in planar and trench power SiC MOSFET devices in extreme short-circuit operation

Abstract

The purpose of this paper is to present a complete experimentation of the two failure modes in competition that can appear during short-circuit (SC) fault operation of single-chip 1,2kV SiC MOSFETs from different manufacturers including planar and trench-gate structures, well-known or recent devices. Ruggedness and selective failure modes are identified in relation with the power density dissipated by the chip and the simulated 1D-thermal junction. Finally, the chips of the devices which failed in a "fail-to-open" mode have been studied in order to find the physical reasons of this original and unusual fail-safe mode.

Thermal simulations of SiC MOSFETs under short-circuit conditions: influence of various simulation parameters

“…The temperature distribution is observed right before catastrophic failure, long after the control over the transistor had been lost -i.e. microseconds after the transistor could safely be turned off [1]. The hottest spot, located few micrometres under the top-side of the die (as already described in [4], [10], [31]), reaches over 1100 K. The temperature field is also shown in the /0, 1-plane.…”

“…As a matter of fact, it could be used to predict the robustness of a circuit and to help understand failure mechanisms such as critical temperatures and heating rates, current crowding, etc. [1], [2]. It could also be used for dieand packaging-design so as to optimise robustness, e.g.…”

Short-circuit robustness of parallel SiC MOSFETs and fail-safe mode strategy

“…Such parallel connection test analysis was performed for two different DUT types from two different manufacturers; Dev-A and Dev-B. Here, the idea was to perform SC tests with an aim of obtaining a soft-fail (drain-source fail-to-open) criteria [8]. Therefore, depending on previous device characterisation of the DUTs as also included in [8,9], the input voltage (VDD) was appropriately adjusted to ensure soft-fail mode at all times.…”

“…Here, the idea was to perform SC tests with an aim of obtaining a soft-fail (drain-source fail-to-open) criteria [8]. Therefore, depending on previous device characterisation of the DUTs as also included in [8,9], the input voltage (VDD) was appropriately adjusted to ensure soft-fail mode at all times. The gate driver circuit schematic which was implemented to perform these tests is presented in Fig.…”

Physical Origin of the Gate Current Surge During Short-Circuit Operation of SiC MOSFET

“…The DUT was tested during SC stress with increasing drain bias until device failure. The experimental setup is described in [10].The waveforms of the SC tests are presented in Fig. 1a.…”