2010
DOI: 10.1016/j.microrel.2010.07.035
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Ageing of SiC JFET transistors under repetitive current limitation conditions

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Cited by 19 publications
(10 citation statements)
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References 9 publications
(13 reference statements)
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“…Characterizations have been performed after the test and a slight reduction of the saturation current of the JFET and a slight increase in the R DSon are noted (see Table I). These results correspond to a normal case [17]. This phenomenon is probably due to ageing of the metallization of the power JFET [18].…”
Section: Resultssupporting
confidence: 75%
“…Characterizations have been performed after the test and a slight reduction of the saturation current of the JFET and a slight increase in the R DSon are noted (see Table I). These results correspond to a normal case [17]. This phenomenon is probably due to ageing of the metallization of the power JFET [18].…”
Section: Resultssupporting
confidence: 75%
“…Such a low heat diffusion distance reveals that the short circuit capability of SiC MOSFETs can be independent of packaging technologies and external cooling conditions. Moreover, the concentrated heat generated within the depletion region could cause the degradation or even damage of the gate oxide and metallization layer [38]. The leakage current of the three devices can be calculated from the junction temperature information.…”
Section: E Simulation Resultsmentioning
confidence: 99%
“…In [8], a 3D model of a SiC JFET, its solder, and base plate is proposed but no other 3D element (e.g. inhomogeneous current distribution) is modelled -except for In [9], a 3D model, including the die, its solder and a baseplate, is used.…”
Section: Literature Reviewmentioning
confidence: 99%
“…SPICE) [5]- [7] or using a dedicated Finite Element (FE) software (e.g. Ansys) [2], [4], [8]- [10]. Although the first approach is a priori much faster, it is usually limited to a few thousands nodes (and often far less), leading to moderate accuracy.…”
Section: Introductionmentioning
confidence: 99%