Error correction based on verification techniques

Huang, Shi-Yu; Chen, Kuang-Chien; Cheng, Kwang-Ting

doi:10.1145/240518.240566

Cited by 20 publications

(15 citation statements)

References 9 publications

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“…These approaches can be divided into two categories with respect to the underlying technique used for error location and error correction: those based on Boolean function manipulation (symbolic) techniques [8]- [11], [16]- [18], [24], [27], [32] and those based on test vector simulation [13]- [15], [21], [22], [25], [26], [28], [29], [33], [34].…”

Section: A Previous Workmentioning

confidence: 99%

“…This is undesirable, as it can jeopardize some of the engineering effort already invested in the design. In the problem of engineering change, one is interested in the least amount of resynthesis on the existing design to obtain one that satisfies the new specification [5], [11], [12], [17].…”

Section: B Engineering Changementioning

confidence: 99%

“…In the first version, a naming equivalence (i.e., functional equivalence) between signals of the new and old specification and the existing design is available from the synthesis process. Existing work [5], [11], [12] uses this information to resynthesize the signals that are not functionally equivalent. In the second version [17], such a naming correspondence is not available as the old and new specification can only provide primary output responses in terms of the primary input stimuli.…”

Section: B Engineering Changementioning

confidence: 99%

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Design error diagnosis and correction via test vector simulation

Veneris

Hajj

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulation-based approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of errors increases. Resynthesis during correction is as little as possible so that most of the engineering effort invested in the design is preserved. Since both steps are based on test vector simulation, the proposed approach is applicable to circuits with no global binary decision diagram representation. Experiments on ISCAS'85 benchmark circuits exhibit the robustness and error resolution of the proposed methodology. Experiments also indicate that test vector simulation is indeed an attractive technique for multiple design error diagnosis and correction in digital VLSI circuits.

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Section: A Previous Workmentioning

confidence: 99%

Section: B Engineering Changementioning

confidence: 99%

Section: B Engineering Changementioning

confidence: 99%

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Design error diagnosis and correction via test vector simulation

Veneris

Hajj

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The third category is called structural approach. This method uses verification techniques to perform a structural comparison between the old and new circuits [3,4,10,11,12]. Although the structural approach is efficient, this method is limited by the similarity between the old and new circuits.…”

Section: Introductionmentioning

confidence: 99%

Interpolation-based incremental ECO synthesis for multi-error logic rectification

Tang

Huang

et al. 2011

Proceedings of the 48th Design Automation Conference

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To cope with last-minute design bugs and specification changes, engineering change order (ECO) is usually performed toward the end of the design process. This paper proposes an automatic ECO synthesis algorithm by interpolation. In particular, we tackle the problem by a series of partial rectifications. At each step, partial rectification can reduce the functional difference between an old implementation and a new specification. Our algorithm is especially effective for multiple error circuits. Experimental results show the proposed method is far superior to the most recent work and scales well on a set of large circuits.

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“…In [4,6,8,15] structural approaches for design error rectification are proposed. Such approaches mostly apply verification techniques to narrow down the potential error region in the implementation.…”

Section: Introductionmentioning

confidence: 99%