Interpolation-based incremental ECO synthesis for multi-error logic rectification

Tang, Kai-Fu; Wu, Chi-An; Huang, Po-Kai; Huang, Chung-Yang

doi:10.1145/2024724.2024758

Cited by 25 publications

(12 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Constraint (27) ensures that each critical gate is assigned to exactly one position. Constraints (28) and (29) guarantee that each tile is occupied by at most one gate.…”

Section: Spare Array Packingmentioning

confidence: 99%

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells

Chang

Jiang

Chang³

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Due to the rapidly increasing design complexity in modern IC designs, metal-only engineering change order (ECO) becomes inevitable to achieve design closure with a low respin cost. Traditionally, preplaced redundant standard cells are regarded as spare cells. However, these cells are limited by predefined functionalities and locations, and they always consume leakage power despite their inputs being tied off. To overcome the inflexibility and power overhead, a new type of spare cells, called metal-configurable gate-array spare cells, are introduced. In this paper, we address a new ECO problem, which performs design changes using metal-configurable gate-array spare cells. We first study the properties of this new ECO problem and propose a new cost metric, aliveness, to model the capability of a spare gate array. Based on aliveness and routability, we then develop two ECO optimization frameworks, one for timing ECO and the other for functional ECO. Experimental results show that our approach delivers superior efficiency and effectiveness.Index Terms-Engineering change order, gate array, mixed integer linear programming

show abstract

“…Constraint (27) ensures that each critical gate is assigned to exactly one position. Constraints (28) and (29) guarantee that each tile is occupied by at most one gate.…”

Section: Spare Array Packingmentioning

confidence: 99%

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells

Chang

Jiang

Chang³

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…One such application is the generation of Craig interpolants that was integrated in variety of logic synthesis algorithms [1][2][3][4]. With this paper we propose a carving interpolation method that overcomes some limitations of the standard Craig interpolation method used for reimplementing a target function with a given set of base functions.…”

Section: Introductionmentioning

confidence: 99%

“…Namely, some synthesis-based Engineering Change Order (ECO) algorithms [4], [5] use Craig interpolation to derive logic circuits, called patches, that make a corrupted implementation functionally equivalent to the wanted one. To maximise the reuse of logic from the old implementation, the patch is built as an interpolant that uses as base functions a set of already implemented functions.…”

Section: Introductionmentioning

confidence: 99%

Constrained interpolation for guided logic synthesis

Petkovska¹,

Novo²,

Mishchenko³

et al. 2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

Abstract-Craig interpolation is a known method for expressing a target function f as a function of a given set of base functions G. The found interpolant represents the dependency function h, such that f = h(G). Generally, the set G contains enough base functions to enable the existence of multiple dependency functions whose quality mainly depends on the base functions selected for reconstruction. The interpolation is not an optimization problem and thus, often, it selects some random base functions and, particularly, omits others potentially required for an optimal implementation of the target function. Mainly, it is impossible to impose that the interpolant uses a specific base function.In this paper, we propose a method that forces a specific base function g i as a primary input of a dependency function. Such dependency function is build as a Shannon expansion of two constrained Craig interpolants for the assignments of the primary inputs for which g i evaluates to 0 and 1, respectively. We also introduce a method that iteratively imposes, one by one, a predefined set of base functions. In each iteration, we force a base function by generating a new dependency function used as a target function for the next iteration.We show that, unlike the standard Craig interpolation method, our carving method succeeds, with very high probability, to impose the desired base functions. It recomposes single-output logic circuits as their delay-or area-optimised implementations regardless of the input implementation. The proposed methods can be efficiently employed for rewriting circuits in some synthesis-based algorithms.

show abstract

“…From a practical perspective, interpolation has been broadly applied to a variety of research areas, especially for logic synthesis and verification, for instance, the computation of functional decomposition [4], [5], the reduction of dynamic power by enlarging clock gating functions [6], and engineering change order [7], [8].…”

Section: Introductionmentioning

confidence: 99%

A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking

Lai

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

Interpolation is an important and distinguished method popularly applied to recent synthesis and verification research topics. Existing approaches generate interpolants by analyzing unsatisfiability (UNSAT) proofs from satisfiable (SAT) solvers. Unfortunately, the interpolant is predestinedly determined by how the UNSAT proof is logged. This particularly weakens the abstraction of interpolation-based model checking procedure. In this paper, a new approach to generate a variety of functionally different interpolants using simulation and SAT solving is proposed. We further seamlessly integrated the novel interpolant generation algorithm into a reinterpreted interpolation-based model checking procedure. Moreover, spurious counterexamples from the model checker further guide the generation of interpolants to refute excessive refinements. As an extra benefit, proof logging is not required for SAT solvers. Experiments show promising results of our interpolationbased model checker NewITP on solving a large set of HWMCC benchmarks.

show abstract

Interpolation-based incremental ECO synthesis for multi-error logic rectification

Cited by 25 publications

References 21 publications

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells

Constrained interpolation for guided logic synthesis

A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking

Contact Info

Product

Resources

About