ECO Optimization Using Metal-Configurable Gate-Array Spare Cells

Abstract

Due to the rapidly increasing design complexity in modern IC designs, metal-only engineering change order (ECO) becomes inevitable to achieve design closure with a low respin cost. Traditionally, preplaced redundant standard cells are regarded as spare cells. However, these cells are limited by predefined functionalities and locations, and they always consume leakage power despite their inputs being tied off. To overcome the inflexibility and power overhead, a new type of spare cells, called metal-configurable gate-array spare cells, are introduced. In this paper, we address a new ECO problem, which performs design changes using metal-configurable gate-array spare cells. We first study the properties of this new ECO problem and propose a new cost metric, aliveness, to model the capability of a spare gate array. Based on aliveness and routability, we then develop two ECO optimization frameworks, one for timing ECO and the other for functional ECO. Experimental results show that our approach delivers superior efficiency and effectiveness.Index Terms-Engineering change order, gate array, mixed integer linear programming

Technology Remapping Approach Using Multi-Gate Reconfigurable Cells for Post-Mask Functional ECO

“…To deal with post-mask ECOs, various approaches that modify only the metal layers have been proposed [4]- [15]. These methods achieve functional and timing modification by placing spare cells in advance at the design stage and using them when post-mask ECO occurs.…”