Design error diagnosis and correction via test vector simulation

Abstract

Abstract-With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulation-based approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of errors increases. Resynthesis during correction is as little as possible so that most of the engineering effort invested in the design is preserved. Since both steps are based on test vector simulation, the proposed approach is applicable to circuits with no global binary decision diagram representation. Experiments on ISCAS'85 benchmark circuits exhibit the robustness and error resolution of the proposed methodology. Experiments also indicate that test vector simulation is indeed an attractive technique for multiple design error diagnosis and correction in digital VLSI circuits.

From RTL to silicon: The case for automated debug

“…Debugging techniques relying on simulation [7]- [10] and BDDs [7], [11] were among the earliest. These solutions perform well under certain conditions but the size of modern designs poses a challenge in their ability to scale.…”

Automatic Fault Localization for Programmable Logic Controllers ★

“…Afterwards, an affect analysis is performed based on path tracing [1], i.e., a path from an observed faulty behavior at an observation point to the primary inputs is computed [21]. The path is extracted by following the controlling values, i.e., the operations that are responsible for the current value at the observation point v f aulty (OP i ).…”

“…All nodes on the sensitive path from any observation point are potential fault candidates. Like for the static analysis, either the intersection or the union is computed for all sensitive paths while assuming single faults or multiple faults, respectively [21].…”

“…[22,2,13,9]) as well as for hardware (e.g. [21,6,17,7]). The aim of automated debugging is the highlighting of potential fault locations to an engineer to reduce the complexity for a subsequent manual debugging session.…”

Fixing Design Errors with Counterexamples and Resynthesis

“…However, fixing errors via resynthesis remains challenging because existing techniques lack the scalability to handle the global implications of the logic modifications imposed by error correction. As a result, state-of-art techniques often limit the types of errors that can be corrected [8] or operate only on small circuits [7], [10].…”