Fixing Design Errors with Counterexamples and Resynthesis

Chang, Kuo–En; Markov, Igor L.; Bertacco, Valeria

doi:10.1109/aspdac.2007.358111

Cited by 51 publications

(39 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Pairs of bits to be distinguished: In [7], it was observed that a set of input signatures S1, ...Sx can implement a target signature S f , if and only if, every pair of different bits in S f is distinguished by at least one Sx. Example 1.…”

Section: Determining Logical Feasibility With Signaturesmentioning

confidence: 99%

See 1 more Smart Citation

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring

Plaza

Markov

Bertacco

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the specified performance objectives. Such iterations are often due to the difficulty of early delay estimation, especially before placement. Therefore, effective logic restructuring to reduce interconnect delay has been a major challenge in physical synthesis, a phase during which more accurate delay estimates can be finally gathered. In this work, we develop a new approach to this problem that enhances modern highperformance logic synthesis techniques with flexibility and accuracy in the physical domain. This approach is based on (1) a novel criterion based on path monotonicity, that identifies those interconnects amenable to optimization through logic restructuring and (2) a synthesis algorithm relying on logic simulation and placement information to identify placed subcircuits that hold promise for interconnect reduction. Experiments indicate that our techniques find optimization opportunities and improve interconnect delay by 11.7% on average at less than 2% wirelength and area overhead.

show abstract

Section: Determining Logical Feasibility With Signaturesmentioning

confidence: 99%

“…The next step enables efficient search for logic transformations. Through logic simulation, we partially characterize the behavior of each node in the subcircuit with a signature [8,7,25]. We then use these signatures to efficiently determine whether a logic transformation generating the desired topology is possible.…”

Section: Introductionmentioning

confidence: 99%

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring

Plaza

Markov

Bertacco

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…The aim of automated debugging is the highlighting of potential fault locations to an engineer to reduce the complexity for a subsequent manual debugging session. Thus, fixing the faulty behavior remains a manual task to avoid unexpected changes that may be introduced by methods that perform repairs automatically [4].…”

Section: Introductionmentioning

confidence: 99%

Automatic Fault Localization for Programmable Logic Controllers ★

Sülflow

Drechsler

2011

Forms/Format 2010

View full text Add to dashboard Cite

Abstract. Programmable Logic Controllers (PLCs) are widely applied to control safety critical systems. Efficient formal and non-formal methods to detect faulty behavior have been developed, but finding the cause of the buggy behavior is often still a manual process. Automatic fault localization for PLCs is studied in this paper. Methods for automated debugging are analyzed and compared with respect to accuracy and run time. The experimental results on industrial models show a high accuracy at low run time costs.

show abstract

“…Based on circuit similarity, the placement and routing of the modified netlist can be derived from the layout of the original netlist obtained in the previous iteration. Unlike many existing algorithms for incremental designs [12,1], which require radical changes to existing computer-aided design (CAD) tools, we have developed a plugin that preserves the "push-button" feature in the commercial FPGA CAD tools.…”

Section: Introductionmentioning

confidence: 99%

“…Each of these steps requires a time-consuming resynthesis of the FPGA design. Incremental design methodology has been devised to save the recompilation time by maintaining the essential properties across consecutive iterations [9,12,23,1,25].…”

Section: Introductionmentioning

confidence: 99%

Enhancement of incremental design for FPGAs using circuit similarity

Shi

Zeng

et al. 2011

2011 12th International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

This paper presents an efficient algorithm to detect the global topological similarity between two circuits. By applying the proposed circuit similarity algorithm in an incremental design flow, IDUCS (incremental design using circuit similarity), the design and optimization effort in the previous design iterations is automatically captured and can be used to guide the next design iteration. IDUCS is able to identify the similarity between the original netlist and the modified one with aggressive resynthesis, which might destroy the naming and local structures of the original netlist. This is superior to the existing design preservation approaches such as naming and local topological matching. Furthermore, IDUCS simply inserts a plugin for circuit similarity detection, and therefore preserves the "push-button" feature, significantly simplifying the engineering complexity of incremental tasks. As a case study, we perform the proposed IDUCS process to generate the placement for a logically resynthesized netlist based on the placement of the original netlist and the circuit similarity between the original and the modified logic-level netlists. The experimental results show our IDUCS-based placement is 28X faster than versatile place and route (VPR) with comparable wire length and estimated critical delay.

show abstract

Fixing Design Errors with Counterexamples and Resynthesis

Cited by 51 publications

References 9 publications

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring

Automatic Fault Localization for Programmable Logic Controllers ★

Enhancement of incremental design for FPGAs using circuit similarity

Contact Info

Product

Resources

About