Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring

Abstract

The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the specified performance objectives. Such iterations are often due to the difficulty of early delay estimation, especially before placement. Therefore, effective logic restructuring to reduce interconnect delay has been a major challenge in physical synthesis, a phase during which more accurate delay estimates can be finally gathered. In this work, we develop a new approach to this problem that enhances modern highperformance logic synthesis techniques with flexibility and accuracy in the physical domain. This approach is based on (1) a novel criterion based on path monotonicity, that identifies those interconnects amenable to optimization through logic restructuring and (2) a synthesis algorithm relying on logic simulation and placement information to identify placed subcircuits that hold promise for interconnect reduction. Experiments indicate that our techniques find optimization opportunities and improve interconnect delay by 11.7% on average at less than 2% wirelength and area overhead.

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths

“…Our algorithm can gain on average 14.1% reduction of circuit delay while the traditional flow only gain 9.2%. The results also show that our algorithm can gain more than 2% delay reduction to [1] (11.7%) with 7 times speedup.…”

“…In [1], the authors use functional simulation for discovering logic transformations. However, the excessive CPU time required restricts its practical usage in large scale circuits (the algorithm takes more than 1000 seconds optimizing a circuit with about only 7000 cells).…”

“…We conduct experiments on several cases from IWLS2005 benchmark suite and compare the results to those by the traditional flow where most critical areas are tackled first and those by a recent work [1] where logic simulation is performed to restructure the circuit for timing optimization. Our algorithm can gain on average 14.1% reduction of circuit delay while the traditional flow only gain 9.2%.…”

On the decreasing significance of large standard cells in technology mapping

“…The arguments from Section 2 suggest that even with placement-driven technology mapping and post-placement logic restructuring, large cells will be less useful on critical paths. An additional advantage of our approach is that breaking down large cells into smaller ones improves routability by enhancing the ability to reduce routing congestion [15][16].…”

“…Recent work [15] points out that conglomerating small cells into a large cell may produce non-monotonic interconnects which adversely affect delay and routability as illustrated in Figure 1. By limiting the use of large standard cells, our approach inherently blocks the occurrence of this disadvantageous technology mapping, and results in a number of shorter monotonic wires.…”