Design error diagnosis in digital circuits with stuck-at fault model

Jutman, Artur; Ubar, Raimund

doi:10.1016/s0026-2714(99)00203-6

Cited by 8 publications

(5 citation statements)

References 17 publications

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“…The proposed algorithm is focused on detecting stuckat-faults that can be mapped to gate replacement faults in logical circuits as proposed in [10], proving set of corollaries for describing mapping from stuck-at-faults into design fault model domain. The following definitions denotes types of design faults: Definition 1 (Gate replacement error).…”

Section: Fault Classesmentioning

confidence: 99%

“…The method of mapping Stuck-at faults into gate-replacement faults is concluded from the following proof in [10]: Therefore, the following set of corollaries describes the mapping process from stuck-at fault model to the design error domain. Also, Fig.…”

Section: Fault Classesmentioning

confidence: 99%

“…In [9], authors used recurrent neural network and dynamic Bayesian modelling for detecting faults in induction motors. Also, stacked autoencoder (AE) was studied in [10] for fault classification of the induction motor. In addition, unsupervised two-layer neural network using the sparse filtering method was proposed in [11] for fault diagnosis.…”

Section: Fault Detection Algorithms Based On Aimentioning

confidence: 99%

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Automated Design Error Debugging of Digital VLSI Circuits

et al. 2022

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As the complexity and scope of VLSI designs continue to grow, fault detection processes in the pre-silicon stage have become crucial to guaranteeing reliability in IC design. Most fault detection algorithms can be solved by transforming them into a satisfiability (SAT) problem decipherable by SAT solvers. However, SAT solvers consume significant computational time, as a result of the search space explosion problem. This ever- increasing amount of data can be handled via machine learning techniques known as deep learning algorithms. In this paper, we propose a new approach utilizing deep learning for fault detection (FD) of combinational and sequential circuits in a type of stuck-at-faults. The goal of the proposed semi-supervised FD model is to avoid the search space explosion problem by taking advantage of unsupervised and supervised learning processes. First, the unsupervised learning process attempts to extract underlying concepts of data using Deep sparse autoencoder. Then, the supervised process tends to describe rules of classification that are applied to the reduced features for detecting different stuck-at faults within circuits. The FD model proposes good performance in terms of running time about 187 × compared to other FD algorithm based on SAT solvers. In addition, it is compared to common classical machine learning models such as Decision Tree (DT), Random Forest (RF) and Gradient Boosting (GB) classifiers, in terms of validation accuracy. The results show a maximum validation accuracy of the feature extraction process at 99.93%, using Deep sparse autoencoder for combinational circuits. For sequential circuits, stacked sparse autoencoder presents 99.95% as average validation accuracy. The fault detection process delivers around 99.6% maximum validation accuracy for combinational circuits from ISCAS’85 and 99.8% for sequential circuits from ISCAS’89 benchmarks. Moreover, the proposed FD model has achieved a running time of about 1.7x, compared to DT classifier and around 1.6x, compared to RF classifier and GB machine learning classifiers, in terms of validation accuracy in detecting faults occurred in eight different digital circuits. Furthermore, the proposed model outperforms other FD models, based on Radial Basis Function Network (RBFN), achieving 97.8% maximum validation accuracy.

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Section: Fault Classesmentioning

confidence: 99%

Section: Fault Classesmentioning

confidence: 99%

Section: Fault Detection Algorithms Based On Aimentioning

confidence: 99%

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Automated Design Error Debugging of Digital VLSI Circuits

et al. 2022

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“…SSBDD is one of the popular model to represent the Boolean function of a Boolean circuit. It keeps the information of circuit structure of digital circuit [8].…”

Section: Introductionmentioning

confidence: 99%

Test Pattern Generation Algorithm Using Structurally Synthesized BDD

Saha¹,

Bisht²,

Yadav³

et al. 2011

JoC

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Structurally Synthesized Binary Decision Diagrams (SSBDDs) have an important characteristic property of keeping information about circuit's structure. Boolean difference of a circuit is used to find test pattern for stuck at fault in combinational circuit but the algebraic manipulation involved in solving Boolean difference is a tedious job. In this paper an efficient algorithm is proposed to compute Boolean difference and test patterns simply using searching the paths of SSBDD. This model reduces algebraic manipulations and takes less time to compute the test pattern.

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“…The PCbased tools installed locally and Java applets invoked remotely via Internet supplement each other and form the engine of the whole concept. The PC-based tool set is called Turbo Tester (TT) [1,7] and consists of the following main tools: test generators based on various algorithms, logic and fault simulators, a test optimizer, a module for hazard analysis [6], a simulator and test generator for defects [2], built-in self-test simulators [4], design verification and design error diagnosis tools [5]. This range of compatible diagnostic tools forms, via their interaction and complementary operation, a homogeneous research environment, which provides good possibilities for laboratory training and experimental research.…”

Section: Introductionmentioning

confidence: 99%